TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 305

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

11.5.9
11.5.10
the bus (the bus is busy), and cleared to "0" when the stop condition is detected (the bus is free).
cycles set by <BC> and <ACK> is completed.
the values specified at SBIxI2CAR or when a general-call (eight bits data following the start condition is all "0")
is received.
to "0", the SBI pulls the SCL line to the "Low" level.
to be released after <PIN> is set to "1". When the program writes "1" to <PIN>, it is set to "1". However, writing
"0" does not clear this bit to "0".
arbitration procedure to ensure correct data transfer.
condition occurring on the SDA and SCL lines.The I2C-bus arbitration takes place on the SDA line.
level and Master B outputs the "High" level.
SBIxSR<BB> can be read to check the bus state. <BB> is set to "1" when the start condition is detected on
In master mode, a serial bus interface request (INTSBIx) is generated when the transfer of the number of clock
In slave mode, INTSBIx is generated under the following conditions.
In the address recognition mode (<ALS> = "0"), INTSBIx is generated when the received slave address matches
When an interrupt request (INTSBIx) is generated, SBIxCR2<PIN> is cleared to "0". While <PIN> is cleared
<PIN> is set to "1" when data is written to or read from SBIxDBR. It takes a period of t
The I2C bus has the multi-master capability (there are two or more masters on a bus), and requires the bus
A master that attempts to generate the start condition while the bus is busy loses bus arbitration, with no start
The arbitration procedure for two masters on a bus is shown below.
Up until the point a, Master A and Master B output the same data. At the point a, Master A outputs the "Low"
Interrupt Service Request and Release
Note:When arbitration is lost in master mode, <PIN> is not cleared to "0" if the slave address does not match
Arbitration Lost Detection Monitor
・ After output of the acknowledge signal which is generated when the received slave address matches
・ After the acknowledge signal is generated when a general-call address is received.
・ When the slave address matches or a data transfer is completed after receiving a general-call address.
the slave address set to SBIxI2CAR<SA[6:0]>.
(INTSBIx is generated).
Figure 11-6 Generating the Stop Condition
SCL line
SDA line
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Stop condition
TMPM330FDFG/FYFG/FWFG
LOW
for the SCL line