TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 490

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

17.3
On-board Programming of Flash Memory (Rewrite/Erase)
(6)
protection bits. If it is desired to stop the operation, use the hardware reset function. When the automatic
operation to erase protection bits is normally terminated, it returns to the read mode.
contained in the device. The data to be loaded will be different depending on the address [15:14] of the
fourth and subsequent bus write cycles (recommended input data is 0x00). On and after the fourth bus
write cycle, when an arbitrary flash memory area is read, the ID value will be loaded. Once the fourth
bus write cycle of an ID-Read command has passed, the device will not automatically return to the read
mode. In this condition, the set of the fourth bus write cycle and ID-Read commands can be repetitively
executed. For returning to the read mode, use the Read/reset command or hardware reset command.
In any case, any new command sequence is not accepted while it is in an automatic operation to erase
Using the ID-Read command, you can obtain the type and other information on the flash memory
Note:The FCFLCS <RDY/BSY> bit is "0" while in automatic operation and it turns to "1" when
ID-Read
・ When FCFLCS <BLPRO> include "0" (not all the protection bits are programmed):
the automatic operation is terminated.
protection bits by FCFLCS <BLPRO> after retuning to the read mode and perform either the
automatic protection bit erase, automatic chip erase, or automatic block erase operation, as
appropriate.
this device, protection bits can be programmed to an individual block and performed bit-erase
operation in the four bits unit as shown in Table 17-19. The target bits are specified in the
seventh bus write cycle.The protection status of each block can be checked by FCFLCS
<BLPRO> to be described later. This status of the programming operation for automatic pro-
tection bits can be checked by monitoring FCFLCS <RDY/BSY>. When the automatic
operation to erase protection bits is normally terminated, the protection bits of FCFLCS
<BLPRO> selected for erasure are set to "0".
If the automatic protection bit is cleared to "0", the protection condition is canceled. With
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TMPM330FDFG/FYFG/FWFG