TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 222
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TMPM330FWFG
Manufacturer Part Number
TMPM330FWFG
Description
Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
Manufacturer
Toshiba
Specifications of TMPM330FWFG
Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
128K
Rom Type
Flash
Ram (kbytes)
8K
Number Of Pins
100
Package
LQFP(14×14)
Vcc
3V
Cpu Mhz
40
Ssp (ch) Spi
-
I2c/sio (ch)
3
Uart/sio (ch)
3
Usb
-
Can
-
Ethernet
-
External Bus Interface
-
Cs/wait Controller (ch)
-
Dma Controller
-
10-bit Da Converter
-
10-bit Ad Converter
12
12-bit Ad Converter
-
16-bit Timer / Counter
10
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / Rohs Status
Details
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Manufacturer
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Price
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9.5
Description of Operations for Each Circuit
9.5.2
9.5.3
built into each channel. If the comparator detects a match between a value set in this timer register and that in a
UC up-counter, it outputs the match detection signal.
fers. The double buffering is disabled in the initial state.
double buffering becomes disable. If <TBWBF> = "1", it becomes enable. When the double buffering is enabled,
a data transfer from the register buffer to the timer register (TBxRG0/1) is done in the case that UC is matched
with TBxRG1.When the counter is stopped even if double buffering is enabled, the double buffering operates as
a single buffer, and an immediate data can be written to the TBxRG0 and TBxRG1.
Up-counter (UC)
Timer registers (TBxRG0, TBxRG1)
UC is a 16-bit binary counter.
TBxRG0 and TBxRG1 are registers for setting values to compare with up-counter values and two registers are
TBxRG0 and TBxRG1 are consisted of the double-buffered configuration which are paired with register buf-
Controlling double buffering disable or enable is specified by TBxCR<TBWBF> bit. If <TBWBF> = "0", the
・ Source clock
・ Count start/ stop
・ Timing to clear UC
・ UC overflow
φT1, φT4 and φT16 - of prescaler output clock or the external clock of the TBxIN0 pin.
stops counting and clears counter value if <TBRUN> = "0".
1. When a match is detected
2. When UC stops
UC source clock, specified by TBxMOD<TBCLK[1:0]>, can be selected from either three types -
Counter operation is specified by TBxRUN<TBRUN>. UC starts counting if <TBRUN> = "1", and
If UC overflow occurs, the INTTBx overflow interrupt is generated.
between counter value and the value set in TBxRG1. UC operates as a free-running counter if
TBxMOD<TBCLE> = "0".
By setting TBxMOD<TBCLE> = "1", UC is cleared if when the comparator detects a match
UC stops counting and clears counter value if TBxRUN<TBRUN> = "0".
Page 202
TMPM330FDFG/FYFG/FWFG
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