TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 347
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TMPM330FWFG
Manufacturer Part Number
TMPM330FWFG
Description
Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
Manufacturer
Toshiba
Specifications of TMPM330FWFG
Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
128K
Rom Type
Flash
Ram (kbytes)
8K
Number Of Pins
100
Package
LQFP(14×14)
Vcc
3V
Cpu Mhz
40
Ssp (ch) Spi
-
I2c/sio (ch)
3
Uart/sio (ch)
3
Usb
-
Can
-
Ethernet
-
External Bus Interface
-
Cs/wait Controller (ch)
-
Dma Controller
-
10-bit Da Converter
-
10-bit Ad Converter
12
12-bit Ad Converter
-
16-bit Timer / Counter
10
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / Rohs Status
Details
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Manufacturer
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Price
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12.3.12
31-23
22-20
19
18-16
15
14-12
11-8
7-5
After reset
After reset
After reset
After reset
bit symbol
bit symbol
bit symbol
bit symbol
Bit
−
CECSTRS[2:0]
−
CECSPRD[2:0]
−
CECDTRS[2:0]
CECDPRD[2:0]
−
Bit Symbol
CECTCR (Transmit Control Register)
31
23
15
0
0
0
7
0
-
-
-
-
R
R/W
R
R/W
R
R/W
R/W
R
Type
30
22
14
0
0
0
6
0
Read as 0.
Rising timing of start bit.
000: Base time
001: Base time− 1/fs
010: Base time− 2/fs
011: Base time− 3/fs
Specifies the rising timing of a start bit.
Base time is 121/fs (approx. 3.693 ms). Enables to specify it between the ranges 0 to −7/fs by the unit of 1/fs.
Read as 0.
Start bit cycle
000: Base time
001: Base time− 1/fs
010: Base time− 2/fs
011: Base time− 3/fs
Specifies a cycle of a start bit.
Base time is 147/fs (approx. 4.486 ms). Enables to specify it between the ranges 0 to −7/fs by the unit of 1/fs.
Read as 0.
Rising timing of data bit.
000: Base time
001: Base time− 1/fs
010: Base time− 2/fs
011: Base time− 3/fs
Specifies the rising timing of a data bit
Base time is 20/fs (approx. 0.610 ms, when logical "1") or 49/fs (approx. 1.495 ms, when logical "0"). Enables
to specify it between the ranges 0 to −3/fs by the unit of 1/fs.
Data bit cycle
0000: Base time
0001: Base time− 1/fs
0010: Base time− 2/fs
0011: Base time− 3/fs
0100: Base time− 4/fs
0101: Base time− 5/fs
0110: Base time− 6/fs
0111: Base time− 7/fs
Specifies a cycle of a data bit.
Base time is 79/fs (approx. 2.411 ms). Enables to specify it between the ranges 0 to −15/fs by the unit of 1/fs.
Read as 0.
-
-
CECSTRS
CECDTRS
29
21
13
0
0
0
5
0
-
-
Page 327
CECBRD
28
20
12
0
0
0
4
0
-
27
19
11
Function
0
0
0
3
0
-
-
100: Base time− 4/fs
101: Base time− 5/fs
110: Base time− 6/fs
111: Base time− 7/fs
100: Base time− 4/fs
101: Base time− 5/fs
110: Base time− 6/fs
111: Base time− 7/fs
100: Reserved
101: Reserved
110: Reserved
111: Reserved
1000: Base time− 8/fs
1001: Base time− 9/fs
1010: Base time− 10/fs
1011: Base time− 11/fs
1100: Base time− 12/fs
1101: Base time− 13/fs
1110: Base time− 14/fs
1111: Base time− 15/fs
26
18
10
0
0
0
2
0
-
TMPM330FDFG/FYFG/FWFG
CECDPRD
CECFREE
CECSPRD
25
17
0
0
9
0
1
0
-
24
16
0
0
8
0
0
0
-
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