TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 233
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TMPM330FWFG
Manufacturer Part Number
TMPM330FWFG
Description
Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
Manufacturer
Toshiba
Specifications of TMPM330FWFG
Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
128K
Rom Type
Flash
Ram (kbytes)
8K
Number Of Pins
100
Package
LQFP(14×14)
Vcc
3V
Cpu Mhz
40
Ssp (ch) Spi
-
I2c/sio (ch)
3
Uart/sio (ch)
3
Usb
-
Can
-
Ethernet
-
External Bus Interface
-
Cs/wait Controller (ch)
-
Dma Controller
-
10-bit Da Converter
-
10-bit Ad Converter
12
12-bit Ad Converter
-
16-bit Timer / Counter
10
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / Rohs Status
Details
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10. Serial Channel (SIO/UART)
10.1
10.2
and the other is the asynchronous communication mode (UART mode).
This device has two mode for the serial channel, one is the synchronous communication mode (I/O interface mode),
Their features are given in the following.
In the following explanation, "x" represents channel number.
TMPM330FDFG/FYFG/FWFG has three SIO channels.
Each channel functions independently. The used pins and interrupt in each channel are collected in the following.
Difference in the Specifications of SIO Modules
・ Transfer Clock
・ Double Buffer /FIFO
・ I/O Interface Mode
・ UART Mode
Overview
4-byte.
-
-
-
-
-
-
-
-
-
-
-
The usable double buffer function, and the usable FIFO buffers of transmit and receive in all for maximum
Dividing by the prescaler, from the peripheral clock (ΦT0) frequency into 1/2, 1/8, 1/32, 1/128.
Make it possible to divide from the prescaler output clock frequency into 1-16.
Make it possible to divide from the prescaler output clock frequency into 1, N+m/16 (N=2-15, m=1-15),
16. (only UART mode)
The usable system clock (only UART mode).
Transfer Mode: the half duplex (transmit/receive), the full duplex
Clock: Output (fixed rising edge) /Input (selectable rising/falling edge)
Make it possible to specify the interval time of continuous transmission.
Data length: 7 bits, 8bits, 9bits
Add parity bit (to be against 9bits data length)
Serial links to use wake-up function
Handshaking function with CTS pin
Table 10-1 Difference in the Specifications of SIO Modules
Pin name
Interrupt
Transmit Interrupt
Receive Interrupt
CTS/SLCK
TXD
RXD
Page 213
PE0(20pin)
PE1(21pin)
PE2(22pin)
Channel 0
INTRX0
INTTX0
PE4(23pin)
PE5(24pin)
PE6(25pin)
Channel 1
INTRX1
INTTX1
PF0(33pin)
PF1(34pin)
PF2(35pin)
Channel 2
INTRX2
INTTX2
TMPM330FDFG/FYFG/FWFG
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