TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 361

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

12.4.3.2
mit Buffer Register (CECTBUF) are required.
(1)
(2)
(3)
Before transmitting data, transmission settings to the Transmit Control Register (CECTCR) and the Trans-
Preconfiguration
Start bit
to 16 bit cycles.
signal stays high for the specified number of bit cycles, transmission starts.
response during an ACK cycle results in an error.If not, logical "1" response during an ACK cycle results
in an error.
<CECSTRS> <CECSPRD> <CECDTRS> <CECDPRD> bits, the timing can be specified between the
defined fastest rising/cycle timing and the reference value.
logical "0" and logical "1".
Specify the bus free wait time in the CECTCR<CECFREE> bits. It can be specified in a range of 1
Counting of the bus free wait time begins one bit cycle after the falling edge of the final bit. If the
Set the CECTCR <CECBRD> bit when transmitting a broadcast message.If this bit is set, logical "0"
Both start bit and data bit are capable of adjusting the rising timing and cycle. With the CECTCR
The following figures show how the waveforms differ according to the configurations of the start bit,
Note:<CECDTRS> must be used under the same setting as CECRCR1<CECLNC>.
Bus Free Wait Time
Adjusting Transmission Waveform
Transmitting Broadcast Message
1bit cycle
Bus free wait time
Page 341
<CECSTRS>
121/fs - 7/fs to 121/fs
(approx.3.693 ms)
Beginning of transmission
TMPM330FDFG/FYFG/FWFG
<CECSPRD>
147/fs - 7/fs to 147/fs
(approx.4.486 ms)