TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 353

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

(3)
(4)
(5)
Data sampring timing that specification recommends
the unit of 1/fs from the minimum value (67/fs, approx. 2.045ms) or the maximum value (90/fs approx.
2.747ms).
bit. The received data is discarded.
fs.
as an ACK response to the data block when destination address corresponds with the address set in the
logical address register.
the addresses corresponding.
(ACK bit: logical "0"). "No" indicates that CEC does not output "0" as a response to the ACK signal
from a transmission device (ACK bit: logical "1").
0 ms
Configure CECRCR1<CECMIN><CECMAX> bits to detect a cycle error.
A cycle error can be detected from each sampling clock cycle between the ranges −4/fs to +3/fs by
Detecting an error during data reception causes an error interrupt, and CEC waits for the next start
Configure the CECRCR1 <CECDAT> bit for the point of determining the data as "0" or "1".
Base time is 34/fs (approx.1.038ms) from the start point and also configurable ±6/fs by the unit of 2/
Configuring the CECRCR1 <CECACKDIS> bit enables you to specify if logical "0" is sent or not
The header block sends logical "0" as an ACK response regardless of the bit setting when detecting
The following lists the ACK responses.
"Yes" indicates that CEC outputs "0" as a response to the ACK signal from a transmission device
Cycle error
Point of Determining Data
ACK Response
0.6 ms
0.85 ms
Recommended period
(approx.1.038ms)
for data sampling
for data sampling
Reference point
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<CECDAT>
34/fs ± 6/fs
1.05 ms
1.25 ms
1.5 ms
TMPM330FDFG/FYFG/FWFG