TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 253

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

10.7
10.7.1
Table 10-4 Clock Resolution to the Baud Rate Generator fc = 40 MHz
peripheral clock
CGSYSCR
<FPSEL>
selection
0 (fgear)
Clock Control
SCxMOD0<SC[1:0]> = "11".
the input clock to the baud rate generator.
There is a 7-bit prescaler to divide a prescaler input clock ΦT0 by 2, 8, 32 and 128.
Use the CGSYSCR register in the clock/mode control block to select the input clock ΦT0 of the prescaler.
The prescaler becomes active only when the baud rate generator is selected as a transfer clock by
Table 10-4 (operation frequency 40MHz), Table 10-5 (operation frequency 32MHz) show the resolution of
Prescaler
<GEAR[2:0]>
CGSYSCR
Clock gear
100 (fc/2)
101 (fc/4)
110 (fc/8)
000 (fc)
value
Prescaler clock se-
100 (fperiph/16)
101 (fperiph/32)
100 (fperiph/16)
101 (fperiph/32)
100 (fperiph/16)
101 (fperiph/32)
100 (fperiph/16)
101 (fperiph/32)
000 (fperiph/1)
001 (fperiph/2)
010 (fperiph/4)
011 (fperiph/8)
000 (fperiph/1)
001 (fperiph/2)
010 (fperiph/4)
011 (fperiph/8)
000 (fperiph/1)
001 (fperiph/2)
010 (fperiph/4)
011 (fperiph/8)
000 (fperiph/1)
001 (fperiph/2)
010 (fperiph/4)
011 (fperiph/8)
<PRCK[2:0]>
CGSYSCR
lection
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
1
9
2
3
4
5
6
2
3
4
5
6
7
3
4
5
6
7
8
4
5
6
7
8
φT1
(0.05 μs)
(12.8 μs)
(0.1 μs)
(0.2 μs)
(0.4 μs)
(0.8 μs)
(1.6 μs)
(0.1 μs)
(0.2 μs)
(0.4 μs)
(0.8 μs)
(1.6 μs)
(3.2 μs)
(0.2 μs)
(0.4 μs)
(0.8 μs)
(1.6 μs)
(3.2 μs)
(6.4 μs)
(0.4 μs)
(0.8 μs)
(1.6 μs)
(3.2 μs)
(6.4 μs)
Page 233
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
Prescaler output clock resolution
10
10
11
9
9
9
3
4
5
6
7
8
4
5
6
7
8
5
6
7
8
6
7
8
φT4
(12.8 μs)
(12.8 μs)
(12.8 μs)
(25.6 μs)
(25.6 μs)
(51.2 μs)
(0.2 μs)
(0.4 μs)
(0.8 μs)
(1.6 μs)
(3.2 μs)
(6.4 μs)
(0.4 μs)
(0.8 μs)
(1.6 μs)
(3.2 μs)
(6.4 μs)
(0.8 μs)
(1.6 μs)
(3.2 μs)
(6.4 μs)
(1.6 μs)
(3.2 μs)
(6.4 μs)
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
TMPM330FDFG/FYFG/FWFG
12
12
13
10
10
11
10
11
10
11
9
9
9
9
φT16
5
6
7
8
6
7
8
7
8
8
(102.4 μs)
(102.4 μs)
(204.8 μs)
(12.8 μs)
(12.8 μs)
(12.8 μs)
(12.8 μs)
(25.6 μs)
(25.6 μs)
(51.2 μs)
(25.6 μs)
(51.2 μs)
(25.6 μs)
(51.2 μs)
(0.8 μs)
(1.6 μs)
(3.2 μs)
(6.4 μs)
(1.6 μs)
(3.2 μs)
(6.4 μs)
(3.2 μs)
(6.4 μs)
(6.4 μs)
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
12
12
13
12
13
14
12
13
14
15
10
11
10
11
10
11
10
11
9
9
9
φT64
7
8
8
(102.4 μs)
(102.4 μs)
(204.8 μs)
(102.4 μs)
(204.8 μs)
(409.6 μs)
(102.4 μs)
(204.8 μs)
(409.6 μs)
(819.2 μs)
(12.8 μs)
(12.8 μs)
(12.8 μs)
(25.6 μs)
(51.2 μs)
(25.6 μs)
(51.2 μs)
(25.6 μs)
(51.2 μs)
(25.6 μs)
(51.2 μs)
(3.2 μs)
(6.4 μs)
(6.4 μs)