TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 262

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

10.9
Status Flag
10.9
10.10
10.10.1
from the receive shift register to the receive buffers, this bit changes to "1" while reading this bit changes it to "0".
shift register, this bit is set to "1" When data is set to the transmit buffers, the bit is cleared to "0".
The table below shows the meanings in each mode.
The SCxMOD2 register has two types of flag. This bit is significant only when the double buffer is enabled.
<RBFLL> is a flag to show that the receive buffer is full. When one frame of data is received and the data is moved
<TBEMP> shows that the transmit buffers are empty. When data in the transmit buffers is moved to the transmit
Three error flags are provided in the SCxCR register. The meaning of the flags is changed depending on the modes.
These flags are cleared to "0" after reading the SCxCR register.
Status Flag
"1". The FIFO buffer configuration is specified by SCxMOD1<FDPX[1:0]>.
reception of the next frame of receive data before the receive buffer has been read. If the receive FIFO is enabled,
the received data is automatically moved to the receive FIFO and no overrun error will be generated until the
receive FIFO is full (or until the usable bytes are fully occupied).
Error Flag
To enable FIFO, enable the double buffer by setting SCxMOD2<WBUF> to "1" and SCxFCNF<CNFG> to
Table 10-11 shows correlation between modes and FIFO.
In both UART and I/O interface modes, this bit is set to "1" when an error is generated by completing the
Note:To use TX/RX FIFO buffer, TX/RX FIFO must be cleared after setting the SIO transfer mode (half duplex/
OERR Flag
(SCLK output)
(SCLK input)
I/O Interface
I/O Interface
full duplex) and enabling FIFO (SCxFCNF<CNFG> = "1").
UART
Mode
Table 10-11 Mode and FIFO Composition
Half duplex RX
Half duplex TX
Full duplex
Overrun error
Overrun error
Undefined
<OERR>
SCxMOD1<FDPX[1:0]>
"01"
"10"
"11"
Page 242
(When using double buffer or
(When a double buffer and
Underrun error
FIFO unused)
Parity error
Undefined
Fixed to 0
<PERR>
FIFO)
RX FIFO
Flag
4byte
2byte
-
TX FIFO
4byte
2byte
-
TMPM330FDFG/FYFG/FWFG
Framing error
Fixed to 0
Fixed to 0
<FERR>