TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 325

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

11.8.2
11.8.2.1
INTSBIx interrupt
SBIxCR1<SIOM[1:0]>.
SBIxCR1
SBIxDBR
SBIxCR1
SBIxDBR
The transmit mode, the receive mode or the transmit/receive mode can be selected by programming
Transfer Modes
is moved from SBIxDBR to a shift register and output to the SO pin, with the least-significant bit (LSB) first,
in synchronization with the serial clock. Once the transmit data is transferred to the shift register, SBIxDBR
becomes empty, and the INTSBIx (buffer-empty) interrupt is generated, requesting the next transmit data.
data is not loaded after the 8-bit data has been fully transmitted. The wait state will be cleared when SBIxDBR
is loaded with the next transmit data.
started. Therefore, the data transfer rate varies depending on the maximum latency between when the interrupt
request is generated and when SBIxDBR is loaded with data in the interrupt service program.
output in a period from setting SBIxSR<SIOF> to "1" to the falling edge of SCK.
interrupt service program. If <SIOS> is cleared, remaining data is output before transmission ends. The
program checks SBIxSR<SIOF> to determine whether transmission has come to an end. <SIOF> is cleared
to "0" at the end of transmission. If <SIOINH> is set to "1", the transmission is aborted immediately and
<SIOF> is cleared to "0".
not be cleared to "0" before next data shifting, SBI output dummy data and stopped.
Set the control register to the transmit mode and write the transmit data to SBIxDBR.
After writing the transmit data, writing "1" to SBIxCR1<SIOS> starts the transmission. The transmit data
In the internal clock mode, the serial clock will be stopped and automatically enter the wait state, if next
In the external clock mode, SBIxDBR must be loaded with data before the next data shift operation is
At the beginning of transmission, the same value as in the last bit of the previously transmitted data is
Transmission can be terminated by clearing <SIOS> to "0" or setting <SIOINH> to "1" in the INTSBIx
When in the external clock mode, <SIOS> must be cleared to "0" before next data shifting. If <SIOS> does
8-bit transmit mode
←
←
←
←
7
0
X
1
X
6
1
X
0
X
5
0
X
0
X
4
0
X
0
X
3
0
X
0
X
2
X
X
X
X
1
X
X
X
X
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0
X
X
X
X
Selects the transmit mode.
Writes the transmit data.
Starts transmission.
Writes the transmit data.
TMPM330FDFG/FYFG/FWFG