TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 315

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

11.6.4
11.6.5
SBIxCR2
start a sequence for generating the stop condition on the bus.
slave device.The procedure of generating a restart in the master mode is described below.
SDAx pin is held at the "High" level and the SCLx pin is released. Because no stop condition is generated on the
bus, other devices recognize that the bus is busy.
the "Low" level.
"11.6.2 Generating the Start Condition and a Slave Address"to generate the start condition.
software after the bus is determined to be free.
Note 1: Do not write <MST> to "0" when it is "0". (Restart cannot be initiated.)
Note 2: When the master device is acting as a receiver, data transmission from the slave device which serves
When SBIxSR<BB> is "1", writing "1" to SBIxCR2<MST, TRX, PIN> and "0" to <BB> causes the SBI to
Do not alter the contents of <MST, TRX, BB, PIN> until the stop condition appears on the bus.
If another device is holding down the SCL bus line, the SBI waits until the SCL line is released.
After that, the SDA pin goes "High", causing the stop condition to be generated.
Restart is used when a master device changes the data transfer direction without terminating the transfer to a
First, write SBIxCR2<MST, TRX, BB> to "0" and write "1" to <PIN> to release the bus. At this time, the
Then, test SBIxSR<BB> and wait until it becomes "0" to ensure that the SCLx pin is released.
Next, test <LRB> and wait until it becomes "1" to ensure that no other device is pulling the SCLx bus line to
Once the bus is determined to be free by following the above procedures, follow the procedures described in
To satisfy the setup time of restart, at least 4.7μs wait period (in the standard mode) must be created by the
Generating the Stop Condition
Restart Procedure
←
as a transmitter must be completed before generating a restart. To complete data transfer, slave
device must receive a "High" level acknowledge signal. For this reason, <LBR> before generating a
7
1
6
1
Figure 11-13 Generating the Stop Condition
"1"→<MST>
"1"→<TRX>
"0"→<BB>
"1"→<PIN>
SCLx pin
SDAx pin
<PIN>
<BB>(Read)
5
0
4
1
3
1
2
0
1
0
0
0
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Generates the stop condition.
Stop condition
TMPM330FDFG/FYFG/FWFG