TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 351

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

12.4
12.4.1
12.4.2
12.4.2.1
Operations
CEC lines are sampled by a 32.768kHz of low speed clock (fs).
Sampling clock
Reception
STAT<CECRISTA> is set.
a received interruption generates. By generating the received interruption, CECRSTAT<CECRIEND> is set.
the CEC circuit internally. This bit is generated from a observation of CEC signal same as other data.
EOM bit set to"1". Detecting the end of last block, CEC becomes the start bit waiting mode.
received data is discarded.
If a start bit is detected, a start bit interruption generates. By generating start bit interruption, CECR-
If one byte data, EOM bit and ACK bit are received, the received data is stored in CECRBUF register, and
In the CECRBUF register, 8 bit data, EOM bit and ACK bit are stored. The ACK bit is not generated in
After one data block is received, receiving operation continues until detecting the last block of data with
Detecting an error during data reception causes an error interrupt, and CEC waits for the next start bit. The
Note:Be careful about the precautions of chapter 12.1.3 in the receive operation.
interrupt
Start bit
Basic Operation
S
H
D1
D2
D3
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D4
Receiving interrupt
Dn-2
TMPM330FDFG/FYFG/FWFG
Dn-1
Dn