TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 257
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TMPM330FWFG
Manufacturer Part Number
TMPM330FWFG
Description
Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
Manufacturer
Toshiba
Specifications of TMPM330FWFG
Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
128K
Rom Type
Flash
Ram (kbytes)
8K
Number Of Pins
100
Package
LQFP(14×14)
Vcc
3V
Cpu Mhz
40
Ssp (ch) Spi
-
I2c/sio (ch)
3
Uart/sio (ch)
3
Usb
-
Can
-
Ethernet
-
External Bus Interface
-
Cs/wait Controller (ch)
-
Dma Controller
-
10-bit Da Converter
-
10-bit Ad Converter
12
12-bit Ad Converter
-
16-bit Timer / Counter
10
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / Rohs Status
Details
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Manufacturer
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10.7.2
10.7.2.1
in which clocks can be selected by the settings of the baud rates generator and modes.
The serial clock circuit is a block to generate transmit and receive clocks (SIOCLK) and consists of the circuits
Serial Clock Generation Circuit
(1)
(2)
The baud rate generator generates transmit and receive clocks to determine the serial channel transfer rate.
Baud Rate Generator
and 128.
SCxBRADD.
mode ,either 1/N or N + (16-K)/16 in the UART mode.
The input clock of the baud rate generator is selected from the prescaler outputs divided by 2, 8, 32
This input clock is selected by setting the SCxBRCR<BRCK>.
The frequency division ratio of the output clock in the baud rate generator is set by SCxBRCR and
The following frequency divide ratios can be used; 1/N frequency division in the I/O interface
The table below shows the frequency division ratio which can be selected.
Note:1/N (N=1)frequency division ratio can be used only when a double buffer is enabled.
Baud Rate Generator input clock
Baud Rate Generator output clock
I/O interface
UART
Mode
Divide Function Setting
SCxBRCR<BRADDE>
N + (16-K)/16 division
Divide by N
Divide by N
Page 237
SCxBRCR<BRS>
1 to 16 (Note)
Divide by N
1 to 16
2 to 15
TMPM330FDFG/FYFG/FWFG
SCxBRADD<BRK>
Divide by K
1 to 15
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