TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 226

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

9.6
Description of Operations for Each Mode
TBxEN
TBxRUN
TBxCR
TBxRG0
TBxRG1
TBxCR
TBxFFCR
TBxMOD
PxCR[m]
PxFR1[m]
TBxRUN
Note 1: m: corresponding bit of port
Note 2: X; Don’t care
The block diagram of this mode is shown below.
Each register in the 16-bit PPG output mode must be programmed as listed below.
TBxRG0
TBxIN0
Write
−; No change
φT16
←
←
←
←
←
←
←
←
←
←
←
←
←
TBxCR<TBWBF>
φT1
φT4
7
1
X
0
*
*
*
*
1
X
X
*
Selector
Selector
6
X
X
0
*
*
*
*
0
X
0
*
Figure 9-4 Block Diagram of 16-bit PPG Mode
5
X
X
−
*
*
*
*
X
0
1
*
Register buffer 0
16-bit comparator
4
X
X
X
*
*
*
*
0
0
0
*
TBxRG0
3
X
X
−
*
*
*
*
0
1
0
*
(** = 01, 10, 11)
2
X
0
X
*
*
*
*
0
1
1
1
16-bit up-counter
Internal data bus
1
X
X
X
*
*
*
*
0
1
*
X
Match
TBxRG1
UC
Write
0
X
0
X
*
*
*
*
0
0
*
1
1
1
Page 206
TBxCR<TBWBF>
Selector
Enables TMRBx operation.
Stops count operation.
Disables double buffering.
Specifies a duty. (16 bits)
Specifies a cycle. (16 bits)
Enables the TBxRG0 double buffering.
(Changes the duty/cycle when the INTTBx interrupt is gener-
ated)
Specifies to trigger TBxFF0 to reverse when a match with
TBxRG0 or TBxRG1 is detected,and sets the initial value of
TBxFF0 to "0."
Designates the prescaler output clock as the input clock,and
disables the capture function.
Allocates corresponding port to TBxOUT.
Starts TMRBx.
TBxRUN<TBRUN>
Register buffer 1
16-bit comparator
Clear
TBxRG1
TBxOUT (PPG output)
TMPM330FDFG/FYFG/FWFG
(TBxFF0)
F/F