TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 252

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

10.6
Data Format
10.6.2
10.6.3
10.6.2.1
10.6.2.2
the SCxMOD2<SBLEN>. The length of the STOP bit data is determined as one-bit when it is received regardless
of the setting of this bit.
The parity bit can be added only in the 7- or 8-bit UART mode.
Setting "1" to SCxCR<PE> enables the parity.
The <EVEN> bit of SCxCR selects either even or odd parity.
The length of the STOP bit in the UART transmission mode can be selected from one bit or two bits by setting
Parity Control
transmit buffer.
mode and SCxMOD<TB8> in the 8-bit UART mode.
in the 8-bit UART mode, it is compared with the one in SCxCR<RB8>.
STOP Bit Length
Upon data transmission, the parity control circuit automatically generates the parity with the data in the
After data transmission is complete, the parity bit will be stored in SCxBUF<TB7> in the 7-bit UART
The <PE> and <EVEN> settings must be completed before data is written to the transmit buffer.
If the received data is moved from the receive shift register to the receive buffer, a parity is generated.
In the 7-bit UART mode, the generated parity is compared with the parity stored in SCxBUF<RB7>, while
If there is any difference, a parity error occurs and the <PERR> of the SCxCR register is set to "1".
In use of the FIFO, <RERR> indicates that a parity error was generated in one of the recieved data.
Transmission
Receiving Data
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TMPM330FDFG/FYFG/FWFG