TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 287
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TMPM330FWFG
Manufacturer Part Number
TMPM330FWFG
Description
Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
Manufacturer
Toshiba
Specifications of TMPM330FWFG
Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
128K
Rom Type
Flash
Ram (kbytes)
8K
Number Of Pins
100
Package
LQFP(14×14)
Vcc
3V
Cpu Mhz
40
Ssp (ch) Spi
-
I2c/sio (ch)
3
Uart/sio (ch)
3
Usb
-
Can
-
Ethernet
-
External Bus Interface
-
Cs/wait Controller (ch)
-
Dma Controller
-
10-bit Da Converter
-
10-bit Ad Converter
12
12-bit Ad Converter
-
16-bit Timer / Counter
10
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / Rohs Status
Details
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Manufacturer
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10.16.2
10.16.3
"01".
controls the parity enable/disable setting.
The length of the stop bit can be specified using SCxMOD2<SBLEN>.
be added and parity enable/disable is controlled using SCxCR<PE>. If <PE> = "1" (enabled), either even or odd
parity can be selected using SCxCR<EVEN>.
The 7-bit UART mode can be selected by setting the serial mode control register (SCxMOD<SM[1:0]>) to
In this mode, parity bits can be added to the transmit data stream; the serial mode control register (SCxCR<PE>)
When <PE> is set to "1" (enable), either even or odd parity may be selected using the SCxCR<EVEN> bit.
The following table shows the control register settings for transmitting in the following data format.
The 8-bit UART mode can be selected by setting SCxMOD0<SM[1:0]> to "10." In this mode, parity bits can
The control register settings for receiving data in the following format are as follows:
Mode 1 (7-bit UART mode)
Mode 2 (8-bit UART mode)
Clocking condi-
tions
SCxMOD0
SCxCR
SCxBRCR
SCxBUF
x : don’t care - : no change
Clocking condi-
start
tions
start
bit 0
bit 0
←
←
←
←
Recetion direction (Reception rate of9600 bps @fc = 9.8304 MHz)
system clock :
High-speed clock gear:
Prescaler clock:
1
System clock:
High-speed clock gear:
Prescaler clock:
7
x
x
0
1
*
2
6
0
1
0
*
2
3
5
1
1
*
-
Page 267
3
(
4
0
x
0
*
4
4
3
0
x
0
*
High-speed (fc)
X1 (fc)
fperiph/2 (fperiph = fsys)
High-speed (fc)
X1
fperiph/2 (fperiph = fsys)
5
2
1
1
x
*
5
6
1
0
0
0
*
6
bps @fc = 9.8304 MHz)
0
1
0
0
*
7
parity
even
parity
odd
Set 7-bit UART mode
Even parity enabled
Set 2400bps
Set transmit data
stop
TMPM330FDFG/FYFG/FWFG
stop
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