TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 358

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

12.4
Operations
(2)
(3)
(4)
interrupt or a minimum cycle error interrupt.
interrupt sets the CECRSTAT <CECRIMIN> bit.
ms from the starting point (the falling edge) of the ACK bit.
If it is "Low", an ACK collision interrupt is generated. If it is "High", and "Low" is detected during the
detection period, the minimum cycle error interrupt is generated. The minimum cycle error causes CEC
to output "Low" for approx. 3.63ms.
reading the data stored in the receive buffer.
interrupt is generated.
At an ACK response, detecting "Low" after the specified period to output generates an ACK collision
The ACK collision interrupt sets the CECRSTAT <CECRIACK> bit. The minimum cycle error
The following describes the period and method of detection.
Detection starts approx. 0.3 ms after the end of the period of outputting "Low" and ends approx 2.0
At 0.3 ms from the end of the period of outputting "Low", CEC checks if the CEC line is "0" or not.
A receive buffer overrun interrupt is generated when the next data reception is completed before
The interrupt sets the CECRSTAT <CECRIOR> bit.
A waveform error occurs when waveform error detection is enabled in CECRCR3.
Detecting a waveform, which does not identical to the defined, results in the waveform error. The
The interrupt sets the CECRSTAT <CECRIWAV> bit.
Receive Buffer Overrun
Waveform Error
Beginning of ACK bit
ACK Collision
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2.0 ms
End of
“Low” output
0.3 ms
Detection
period
TMPM330FDFG/FYFG/FWFG