TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 115

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

31
30-28
27-26
25
24
23
22-20
19-18
17
16
15
14-12
11-10
9
After reset
After reset
After reset
After reset
bit symbol
bit symbol
bit symbol
bit symbol
Bit
7.6.3.2
−
EMCG7[2:0]
EMST7[1:0]
−
INT7EN
−
EMCG6[2:0]
EMST6[1:0]
−
INT6EN
−
EMCG5[2:0]
EMST5[1:0]
−
Bit Symbol
CGIMCGB(CG Interrupt Mode Control Register B)
31
23
15
0
0
0
7
0
-
-
-
-
R
R/W
R
R
R/W
R
R/W
R
R
R/W
R
R/W
R
R
Type
30
22
14
0
0
0
6
0
Read as 0.
active level setting of INTRMCRX0 standby clear request
Set it as shown below.
011: Rising edge
active level of INTRMCRX0 standby clear request
00: −
01: Rising edge
10: Falling edge
11: Both edges
Reads as undefined.
INTRMCRX0 clear input
0:Disable
1: Enable
Read as 0.
active level setting of INTCECRX standby clear request
Set it as shown below.
011: Rising edge
active level of INTCECRX standby clear request
00: −
01: Rising edge
10: Falling edge
11: Both edges
Reads as undefined.
INTCECRX clear input
0:Disable
1: Enable
Read as 0.
active level setting of INT5 standby clear request (101~111: setting prohibited)
000: "Low" level
001: "High" level
010: Falling edge
011: Rising edge
100: Both edges
active level of INT5 standby clear request
00: −
01: Rising edge
10: Falling edge
11: Both edges
Reads as undefined.
EMCG7
EMCG6
EMCG5
EMCG4
29
21
13
1
1
1
5
1
Page 95
28
20
12
0
0
0
4
0
27
19
11
Function
0
0
0
3
0
EMST7
EMST6
EMST5
EMST4
26
18
10
0
0
0
2
0
TMPM330FDFG/FYFG/FWFG
Undefined
Undefined
Undefined
Undefined
25
17
9
1
-
-
-
-
INT7EN
INT6EN
INT5EN
INT4EN
24
16
0
0
8
0
0
0