TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 357

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

12.4.2.3
12.4.2.4
12.4.2.5
ception by enabling the CECREN <CECREN> bit. Detecting a start bit initiates the reception.
received data is discarded.
form error), continue reception and send the reversed ACK response.
interrupt.
(1)
After configuring the CECADD, CECRCR1, CECRCR2 and CECRCR3 registers, CEC is ready for re-
Detecting an error during data reception causes an error interrupt, and CEC waits for the next start bit. The
It is possible to suspend a receive error interrupt (maximum cycle error, receive buffer overrun and wave-
You can check the interrupt factor by monitoring the bit of the CECRSTAT register corresponding to the
Note:Changing the configurations of the CECADD, CECRCR1, CECRCR2 and CECRCR3 registers during
Enabling Reception
Detecting Error Interrupt
Details of reception error
does not comply with the specified minimum or maximum value, a cycle error interrupt is generated.
<CECMAX> bits. Maximum value is 90/fs (approx.2.747ms) and minimum value is 67/fs (approx.
2.045ms). It can be specified between the ranges −4/fs to +3/fs by the unit of 1/fs to detect cycle errors.
generated.
reception may harm its proper operation. Before the change of the registers shown below, set the
CECREN <CECREN> bit to disable the reception and read the <CECREN> bit and the CECTEN
<CECTRANS> bit to ensure that the operation is stopped.
Note 1: When minimum cycle error is detected, "Low" is output after "Low" detecting noise cancellation time.
Note 2: If the initiator sends a new message beginning with the start bit without having sent the last block with
CECADD
CECRCR1
CECRCR2
CECRCR3
Period between the falling edges of the two sequential bits is measured during reception. If the period
A setting of maximum cycle and minimum cycle time is specified by CECRCR1<CECMIN> and
The CECRSTAT <CECRIMIN> bit or the <CECRIMAX> bit is set if a cycle error interrupt is
The minimum cycle error causes CEC to output "Low" for approx. 3.63 ms.
Register name
Cycle error
EOM="1", a maximum cycle error may be determined for the ACK bit. For detail , refer to the Chapter
12.1.3.
<CECADD[15:0]>
<CECHNC><CECLNC>
<CECMIN><CECMAX>
<CECOTH>
<CECSWAV0><CECSWAV1>
<CECSWAV2><CECSWAV3>
<CECWAV0><CECWAV1>
<CECWAV2><CECWAV3>
Bit Symbol
Page 337
Logical address
Noise cancellation time
Time to identify cycle error
Data reception at logical address discrep-
ancy
Start bit detection
Waveform error detection (when enabled)
Setting item
TMPM330FDFG/FYFG/FWFG