TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 377

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

13.3.11
31-16
15
14
13
12
11-8
7
6-0
After reset
After reset
After reset
After reset
bit symbol
bit symbol
bit symbol
bit symbol
Bit
−
RMCRLIF
RMCLOIF
RMCDMAXIF
RMCEDIF
−
RMCRLDR
RMCRNUM[6:0]
Note 1: This register is updated every time an interrupt is generated.Writing to this register is ignored.
Note 2: RMC keeps receiving 73 bit or more data unless reception is completed by detecting the maximum data bit
Bit Symbol
RMCxRSTAT (Receive Status Register)
RMCRLDR
RMCRLIF
31
23
15
0
0
0
7
0
-
-
cycle or the excess low width. If so, the received data in the data buffer may not be correct.
R
R
R
R
R
R
R
R
Type
RMCLOIF
30
22
14
0
0
0
6
0
-
-
Read as 0.
Interrupt source flag
0: No leader detection interrupt generated.
1: Leader detection interrupt generated.
Interrupt source flag
0: No low width detection interrupt generated.
1: Low width detection interrupt generated.
Interrupt source flag
0: No maximum data bit cycle interrupt generated.
1: Maximum data bit cycle interrupt generated.
Interrupt source flag
0: No falling edge interrupt generated.
1: Falling edge interrupt generated.
Read as 0.
Leader detection.
0: Disable leader detection.
1: Enable leader detection.
The number of received data bit
000_0000:no data bit (only with leader)
000_0001 to 100_1000: 1 to 72bit
100_1001 to 111_1111: 73bit and more
Indicates the number of bits received as remote control signal data. The number cannot be monitored
during reception. On completion of reception, the number is stored.
RMCDMAXIF
29
21
13
0
0
0
5
0
-
-
Page 357
RMCEDIF
28
20
12
0
0
0
4
0
-
-
RMCRNUM
27
19
11
0
0
0
3
0
-
-
-
Function
26
18
10
0
0
0
2
0
-
-
-
TMPM330FDFG/FYFG/FWFG
25
17
0
0
9
0
1
0
-
-
-
24
16
0
0
8
0
0
0
-
-
-