TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 229

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

[Main processing] Capture setting by TBxIN0
[Processing of INTCAPx0 interrupt service routine] Pulse output setting
[Processing of INTTBx interrupt service routine] Output disable
Figure 9-6 One-shot Pulse Output Triggered by an External Pulse (Without Delay)
PxIE[m]
PxFR1[m]
TBxEN
TBxRUN
TBxMOD
TBxFFCR
PxCR[m]
PxFR1[m]
Interrupt Set-Enable
Register
TBxRUN
TBxRG0
TBxRG1
TBxFFCR
TBxIM
Interrupt Set-Enable
Register
TBxFFCR
Interrupt enable clear
register
TBxIN0 input at the rising edge. (ΦT1 is selected for counting.)
of the TBxCP0 value (c) and the one-shot pulse width (p), (c + p), by generating the INTCAPx0 interrupt.
(TBxRG1 change must be completed before the next match.)
interrupt.
Note 1: m: corresponding bit of port
Note 2: X; Don’t care −; No change
The followings show the settings in the case that 2 ms width one-shot pulse is output after 3ms by triggering
Changes source clock to ΦT1. Fetches a count value into the TBxCP0 at the rising edge of TBxIN0.
If a delay is not required, TBxFF0 is reversed when data is taken into TBxCP0, and TBxRG1 is set to the sum
TBxFF0 is enabled to reverse when UC matches with TBxRG1, and is disabled by generating the INTTBx
Count clock
(Prescaler output
TBxIN0 input
(External trigger pulse)
Match with TBxRG1
Timer output
clock)
TBxOUT pin
Enable reverse when data
is taken into TBxCP0.
←
←
← 1
← X
← X
← X
←
←
← *
← *
← *
← *
← X
← X
← *
← X
← *
7
6
X
X
0
X
*
*
*
*
X
X
*
X
*
5
X
X
1
0
*
*
*
*
−
X
*
−
*
c
4
X
X
0
0
*
*
*
*
−
X
*
−
*
Enable reverse
Taking data into the capture register TBxCP0.
INTCAPx0
generation
Pulse width
3
X
X
1
0
*
*
*
*
1
X
*
0
*
(p)
2
X
0
0
0
*
1
*
*
1
1
*
0
*
Page 209
1
X
X
0
1
*
X
*
*
−
0
*
−
*
0
1
1
X
0
1
0
1
1
*
1
*
*
−
1
*
−
*
c + p
INTTBx
generation
Allocates corresponding port to TBxIN0.
Enables TMRBx operation.
Stops count operation.
Changes source clock to ΦT1. Fetches a count value into the
TBxCP0 at the rising edge of TBxIN0.
Clears TBxFF0 reverse trigger and disables.
Allocates corresponding port toTBxOUT.
Permits to generate interrupts specified by INTCAPx0 interrupt
corresponding bit by setting to "1".
Starts the TMRBx module.
Sets count value. (TBxCAP0 + 3ms/ΦT1)
Sets count value.(TBxCAP0 + (3+2)ms/ΦT1)
Reverses TBxFF0 if TBxRG0 consistent with TBxRG1.
Masks except TBxRG1 correspondence interrupt.
Permits to generate interrupt specified by INTTBx interrupt cor-
responding bit setting to "1".
Clears TBxFF0 reverse trigger setting.
Prohibits interrupts specified by INTTBx interrupt correspond-
ing bit by setting to "1".
Disable reverse when data
is taken into TBxCP1.
Taking data into the capture
register TBxCP1.
TMPM330FDFG/FYFG/FWFG