TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 378

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

13.4
Operation Description
13.4
13.4.1
13.4.1.1
13.4.1.2
Data reception completed by dstecting the max data bit cycle
Operation Description
Reception of Remote Control Signal
detecting. When a leader detection interrupt generates, RMCxRSTAT<RMCRLIF> bit is set.
RMCxRBUF1, RMCxRBUF2 and RMCxRBUF3 registers up to 72 bits. By setting RMCxRCR2< RMCE-
DIEN> bit, a remote control signal input falling edge interrupt can be generated in each falling edge of data
bit. When a remote control signal input falling edge interrupt is generated, RMCxRSTAT< RMCEDIF > bit
is set.
terrupt.
reception without detecting a leader.
overwritten by the next one.
Waiting for leader
A remote control signal is sampled by low-speed 32.768kHz clock (fs).
RMC set RMCxRSTAT<RMCRLDR> bit when a leader is detected.
At this time, if RMCxRCR2<RMCLIEN> bit is set, a leader detection interrupt will generate when a leader
After the leader detecting, each data bit is determined as "0" or "1" in sequence. The results are stored in
Detecting the maximum data bit cycle or the excess low width completes reception and generates an in-
To check the status of RMC if reception is completed, read the remote control receive status register.
On completion of reception, RMC is waiting for the next leader.
By setting RMC to receive a signal without a leader, RMC recognizes the received as data and starts
If the next data reception is completed before reading the preceding received data, the preceding data is
Sampling clock
Basic operation
Detecting leader
Capable of receiving data up to 72bit
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Specified period of a maximum data bit cycle
The maximum data bit cycle interrupt
TMPM330FDFG/FYFG/FWFG
Waiting for leader