TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 360

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

12.4
Operations
12.4.3
12.4.3.1
Wait for bus
to be free
Transmission
signals is not existed for specified bit cycles and then sends a start bit. The confirmation of bus free wait is
performed all the time. Thus once bus free wait condition is satisfied, a transmission will start soon when
transmission setting is done.
buffer to the shift register. When the transmission of the first bit of the one byte data begins, transmission
interrupt is generates, and CECTSTAT<CECTISTA> is set. After transmission interrupt generation, next one
byte data is prepared to the transmit data buffer.
and ACK bit response confirmation.
transmission and ACK bit response. By the end of transmission interrupt generates, CECTSTAT<CEC-
TIEND> is set.
In the transmission setting, CEC firstly confirms bus free wait state to check whether CEC falling edge
After transmitting a start bit, CEC transmits one byte data and EOM data that are stored in the transmit
One byte data transmission completes in order of transmission of 8 bits data, EOM bit, ACK bit transmission
Data transmission continues until EOM is set to "1".
If EOM is set to "1", the end of transmission interrupt generates after confirmation of data, EOM, ACK bit
Interrupt generation ends a series of transmission process, and CECTEN<CECTEN> is cleared.
If an error is generated during transmission, an error interrupt is generates to stop transmission.
Even if reception is enabled, no reception is executed during transmission.
Basic Operation
S
H
D1
D2
(beginning of transmission)
Transmit interrupt
D3
Page 340
D4
Dn-2
TMPM330FDFG/FYFG/FWFG
(end of transmission)
Transmit interrupt
Dn-1
Dn