TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 81

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

(2)
(3)
(4)
table is located at address 0x0000_0000 in the Code area.By setting the Vector Table Offset Register,
you can place the vector table at any address in the Code or SRAM space.
CPU handles the higher priority exception first. This is called "late-arriving".
sponding ISR, but the CPU does not newly push the register contents to the stack.
Hard Fault ISR address).Set ISR addresses for other exceptions if necessary.
0x00
0x04
0x08
0x0C
0x10
0x14
0x18
0x1C ~ 0x28
0x2C
0x30
0x34
0x38
0x3C
0x40
The CPU enables instruction to fetch the interrupt processing with data store to the register.
Prepare a vector table containing the top addresses of ISRs for each exception.After reset, the vector
The vector table should also contain the initial value of the main stack.
If the CPU detects a higher priority exception before executing the ISR for a previous exception, the
A late-arriving exception causes the CPU to fetch a new vector address for branching to the corre-
The vector table is configured as shown below.
You must always set the first four words (stack top address, reset ISR address, NMI ISR address, and
Fetching an ISR
Late-arriving
Vector table
Offset
Reset
Reset
Non-Maskable Interrupt
Hard Fault
Memory Management
Bus Fault
Usage Fault
Reserved
SVCall
Debug Monitor
Reserved
PendSV
SysTick
External Interrupt
Exception
Old SP →
SP →
Page 61
Initial value of the main stack
ISR address
ISR address
ISR address
ISR address
ISR address
ISR address
ISR address
ISR address
ISR address
ISR address
ISR address
<previous>
xPSR
PC
r12
LR
r3
r2
r1
r0
Contents
TMPM330FDFG/FYFG/FWFG
Required
Required
Required
Required
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Setting