TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 18

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

15. Watchdog Timer(WDT)
16. Real Time Clock (RTC)
x
14.4 Description of Operations....................................................................................................390
15.1 Configuration.......................................................................................................................399
15.2 Register................................................................................................................................400
15.3 Operations............................................................................................................................402
15.4 Operation when malfunction (runaway) is detected............................................................403
15.5 Control register....................................................................................................................405
16.1 Function...............................................................................................................................407
16.2 Block Diagram.....................................................................................................................407
16.3 Detailed Description Register..............................................................................................408
16.4 Operational Description.......................................................................................................417
14.3.19
14.3.20
14.4.1
14.4.2
14.4.3
14.4.4
14.4.5
15.2.1
15.2.2
15.3.1
15.3.2
15.4.1
15.4.2
15.5.1
15.5.2
15.5.3
16.3.1
16.3.2
16.3.3
16.4.1
16.4.2
16.4.3
14.4.2.1
14.4.2.2
14.4.5.1
14.4.5.2
14.4.5.3
14.4.5.4
14.4.5.5
14.4.5.6
14.4.5.7
15.5.3.1
15.5.3.2
15.5.3.3
15.5.3.4
16.3.3.1
16.3.3.2
16.3.3.3
16.3.3.4
16.3.3.5
16.3.3.6
16.3.3.7
16.3.3.8
16.3.3.9
16.3.3.10
16.3.3.11
Analog Reference Voltage.............................................................................................................................................390
AD Conversion Mode....................................................................................................................................................390
AD Monitor Function....................................................................................................................................................391
Selecting the Input Channel...........................................................................................................................................392
AD Conversion Details..................................................................................................................................................392
WDMOD(Watchdog Timer Mode Register) ................................................................................................................400
WDCR (Watchdog Timer Control Register).................................................................................................................401
Basic Operation..............................................................................................................................................................402
Operation Mode and Status............................................................................................................................................402
INTWDT interrupt generation.......................................................................................................................................403
Internal reset generation.................................................................................................................................................404
Watchdog Timer Mode Register (WDMOD)................................................................................................................405
Watchdog Timer Control Register(WDCR)..................................................................................................................405
Setting example..............................................................................................................................................................406
Register List...................................................................................................................................................................408
Control Register.............................................................................................................................................................408
Detailed Description of Control Register......................................................................................................................410
Reading clock data.........................................................................................................................................................417
Writing clock data..........................................................................................................................................................417
Entering the Low Power Consumption Mode...............................................................................................................419
ADCMP0 (AD Conversion Result Comparison Register 0).......................................................................................389
ADCMP1 (AD Conversion Result Comparison Register 1).......................................................................................389
Normal AD conversion
Top-priority AD conversion
Starting AD Conversion
AD Conversion
Top-priority AD conversion during normal AD conversion
Stopping Repeat Conversion Mode
Reactivating normal AD conversion
Conversion completion
Interrupt generation timings and AD conversion result storage register
Disabling control
Enabling control
Watchdog timer clearing control
Detection time of watchdog timer
RTCSECR (Second column register (for PAGE0 only))
RTCMINR (Minute column register (PAGE0/1))
RTCHOURR (Hour column register(PAGE0/1))
RTCDAYR (Day of the week column register(PAGE0/1))
RTCDATER (Day column register (for PAGE0/1 only))
RTCMONTHR (Month column register (for PAGE0 only))
RTCMONTHR (Selection of 24-hour clock or 12-hour clock24(for PAGE1 only))
RTCYEARR (Year column register (for PAGE0 only))
RTCYEARR (Leap year register (for PAGE1 only))
RTCPAGER(PAGE register(PAGE0/1))
RTCRESTR (Reset register (for PAGE0/1))