PIC18F4580-I/P Microchip Technology Inc., PIC18F4580-I/P Datasheet - Page 77

• Manufacturer Part Number: PIC18F4580-I/P
• Description: 40 PIN, 32 KB FLASH, 1536 RAM, 36 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F4580-I/P

• A/d Inputs: 11-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 36
• Interface: CAN/I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 32K Bytes
• Ram Size: 1.5K Bytes
• Speed: 40 MHz
• Timers: 1-8 bit, 3-16 bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

7.0
7.1
An 8 x 8 hardware multiplier is included in the ALU of
the PIC18FXX8 devices. By making the multiply a
hardware operation, it completes in a single instruction
cycle. This is an unsigned multiply that gives a 16-bit
result. The result is stored in the 16-bit product register
pair (PRODH:PRODL). The multiplier does not affect
any flags in the ALUSTA register.
Making the 8 x 8 multiplier execute in a single cycle
gives the following advantages:
• Higher computational throughput
• Reduces code size requirements for multiply
The performance increase allows the device to be used
in applications previously reserved for Digital Signal
Processors.
Table 7-1 shows a performance comparison between
Enhanced devices using the single-cycle hardware
multiply and performing the same function without the
hardware multiply.
TABLE 7-1:
 2004 Microchip Technology Inc.
16 x 16 unsigned
algorithms
8 x 8 unsigned
16 x 16 signed
8 x 8 signed
Routine
8 x 8 HARDWARE MULTIPLIER
Introduction
PERFORMANCE COMPARISON
Without hardware multiply
Without hardware multiply
Without hardware multiply
Without hardware multiply
Hardware multiply
Hardware multiply
Hardware multiply
Hardware multiply
Multiply Method
Program
Memory
(Words)
13
33
21
24
52
36
1
6
7.2
Example 7-1 shows the sequence to do an 8 x 8
unsigned multiply. Only one instruction is required
when one argument of the multiply is already loaded in
the WREG register.
Example 7-2 shows the sequence to do an 8 x 8 signed
multiply. To account for the sign bits of the arguments,
each argument’s Most Significant bit (MSb) is tested
and the appropriate subtractions are done.
EXAMPLE 7-1:
EXAMPLE 7-2:
MOVF
MULWF
MOVF
MULWF
BTFSC
SUBWF
MOVF
BTFSC
SUBWF
Cycles
(Max)
242
254
69
91
24
36
1
6
Operation
ARG1, W
ARG2
ARG1, W
ARG2
ARG2, SB
PRODH
ARG2, W
ARG1, SB
PRODH
@ 40 MHz
24.2 s
25.4 s
100 ns
600 ns
6.9 s
9.1 s
2.4 s
3.6 s
8 x 8 UNSIGNED
MULTIPLY ROUTINE
8 x 8 SIGNED MULTIPLY
ROUTINE
PIC18FXX8
;
; ARG1 * ARG2 ->
;
; ARG1 * ARG2 ->
; PRODH:PRODL
; Test Sign Bit
; PRODH = PRODH
;
; Test Sign Bit
; PRODH = PRODH
;
@ 10 MHz
102.6 s
PRODH:PRODL
27.6 s
36.4 s
96.8 s
14.4 s
Time
400 ns
2.4 s
9.6 s
DS41159D-page 75
- ARG1
- ARG2
@ 4 MHz
242 s
254 s
69 s
91 s
24 s
36 s
1 s
6 s