PIC18F4580-I/P Microchip Technology Inc., PIC18F4580-I/P Datasheet - Page 173
PIC18F4580-I/P
Manufacturer Part Number
PIC18F4580-I/P
Description
40 PIN, 32 KB FLASH, 1536 RAM, 36 I/O
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F4580-IP.pdf
(402 pages)
Specifications of PIC18F4580-I/P
A/d Inputs
11-Channel, 10-Bit
Comparators
2
Cpu Speed
10 MIPS
Eeprom Memory
256 Bytes
Input Output
36
Interface
CAN/I2C/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
40-pin PDIP
Programmable Memory
32K Bytes
Ram Size
1.5K Bytes
Speed
40 MHz
Timers
1-8 bit, 3-16 bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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17.4.8
To initiate a Start condition, the user sets the Start
condition enable bit, SEN (SSPCON2<0>). If the SDA
and SCL pins are sampled high, the Baud Rate Gener-
ator is reloaded with the contents of SSPADD<6:0>
and starts its count. If SCL and SDA are both sampled
high when the Baud Rate Generator times out (T
the SDA pin is driven low. The action of the SDA being
driven low, while SCL is high, is the Start condition and
causes the S bit (SSPSTAT<3>) to be set. Following
this, the Baud Rate Generator is reloaded with the
contents of SSPADD<6:0> and resumes its count.
When the Baud Rate Generator times out (T
SEN bit (SSPCON2<0>) will be automatically cleared
by hardware, the Baud Rate Generator is suspended,
leaving the SDA line held low and the Start condition is
complete.
FIGURE 17-19:
2004 Microchip Technology Inc.
Note:
I
CONDITION TIMING
If, at the beginning of the Start condition,
the SDA and SCL pins are already sam-
pled low, or if during the Start condition, the
SCL line is sampled low before the SDA
line is driven low, a bus collision occurs;
the Bus Collision Interrupt Flag, BCLIF, is
set, the Start condition is aborted and the
I
2
2
C module is reset into its Idle state.
C MASTER MODE START
Write to SEN bit occurs here
FIRST START BIT TIMING
SDA
SCL
BRG
SDA = 1,
SCL = 1
T
BRG
), the
BRG
),
Set S bit (SSPSTAT<3>)
T
S
BRG
At completion of Start bit,
hardware clears SEN bit
17.4.8.1
If the user writes the SSPBUF when a Start sequence
is in progress, the WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
and sets SSPIF bit
Note:
T
Write to SSPBUF occurs here
BRG
1st bit
Because queueing of events is not
allowed, writing to the lower 5 bits of
SSPCON2 is disabled until the Start
condition is complete.
WCOL Status Flag
T
BRG
PIC18FXX8
2nd bit
DS41159D-page 171
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