PIC18F4580-I/P Microchip Technology Inc., PIC18F4580-I/P Datasheet - Page 240

• Manufacturer Part Number: PIC18F4580-I/P
• Description: 40 PIN, 32 KB FLASH, 1536 RAM, 36 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F4580-I/P

• A/d Inputs: 11-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 36
• Interface: CAN/I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 32K Bytes
• Ram Size: 1.5K Bytes
• Speed: 40 MHz
• Timers: 1-8 bit, 3-16 bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

FIGURE 19-10:
19.13 CAN Interrupts
The module has several sources of interrupts. Each of
these interrupts can be individually enabled or
disabled. The CANINTF register contains interrupt
flags. The CANINTE register contains the enables for
the 8 main interrupts. A special set of read-only bits in
the CANSTAT register, the ICODE bits, can be used in
combination with a jump table for efficient handling of
interrupts.
All interrupts have one source, with the exception of the
error interrupt. Any of the error interrupt sources can set
the error interrupt flag. The source of the error interrupt
can be determined by reading the Communication
Status register, COMSTAT.
The interrupts can be broken up into two categories:
receive and transmit interrupts.
The receive related interrupts are:
• Receive Interrupts
• Wake-up Interrupt
• Receiver Overrun Interrupt
• Receiver Warning Interrupt
• Receiver Error-Passive Interrupt
The transmit related interrupts are:
• Transmit Interrupts
• Transmitter Warning Interrupt
• Transmitter Error-Passive Interrupt
• Bus-Off Interrupt
DS41159D-page 238
PIC18FXX8
RXERRCNT < 127 or
TXERRCNT < 127
ERROR MODES STATE DIAGRAM
Passive
Error-
TXERRCNT > 255
RXERRCNT > 127 or
TXERRCNT > 127
Active
Error-
19.13.1
The source of a pending interrupt is indicated in the
ICODE (Interrupt Code) bits of the CANSTAT register
(ICODE<2:0>). Interrupts are internally prioritized such
that the higher priority interrupts are assigned lower
ICODE values. Once the highest priority interrupt con-
dition has been cleared, the code for the next highest
priority interrupt that is pending (if any) will be reflected
by the ICODE bits (see Table 19-3, following page).
Note that only those interrupt sources that have their
associated CANINTE enable bit set will be reflected in
the ICODE bits.
19.13.2
When the transmit interrupt is enabled, an interrupt will
be generated when the associated transmit buffer
becomes empty and is ready to be loaded with a new
message. The TXBnIF bit will be set to indicate the
source of the interrupt. The interrupt is cleared by the
MCU resetting the TXBnIF bit to a ‘0’.
19.13.3
When the receive interrupt is enabled, an interrupt will
be generated when a message has been successfully
received and loaded into the associated receive buffer.
This interrupt is activated immediately after receiving
the EOF field. The RXBnIF bit will be set to indicate the
source of the interrupt. The interrupt is cleared by the
MCU resetting the RXBnIF bit to a ‘0’.
Bus-
Off
INTERRUPT CODE BITS
TRANSMIT INTERRUPT
RECEIVE INTERRUPT
Reset
128 occurrences of
11 consecutive
“recessive” bits
 2004 Microchip Technology Inc.