PIC18F4580-I/P Microchip Technology Inc., PIC18F4580-I/P Datasheet - Page 279
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PIC18F4580-I/P
Manufacturer Part Number
PIC18F4580-I/P
Description
40 PIN, 32 KB FLASH, 1536 RAM, 36 I/O
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F4580-IP.pdf
(402 pages)
Specifications of PIC18F4580-I/P
A/d Inputs
11-Channel, 10-Bit
Comparators
2
Cpu Speed
10 MIPS
Eeprom Memory
256 Bytes
Input Output
36
Interface
CAN/I2C/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
40-pin PDIP
Programmable Memory
32K Bytes
Ram Size
1.5K Bytes
Speed
40 MHz
Timers
1-8 bit, 3-16 bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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24.4.1
The user memory may be read to or written from any
location using the table read and table write instruc-
tions. The device ID may be read with table reads. The
Configuration registers may be read and written with
the table read and table write instructions.
In user mode, the CPn bits have no direct effect. CPn
bits inhibit external reads and writes. A block of user
memory may be protected from table writes if the
WRTn configuration bit is ‘0’. The EBTRn bits control
table reads. For a block of user memory with the
EBTRn bit set to ‘0’, a table read instruction that
executes from within that block is allowed to read. A
table read instruction that executes from a location
outside of that block is not allowed to read and will
result in reading ‘0’s. Figures 24-4 through 24-6
illustrate table write and table read protection.
FIGURE 24-4:
2004 Microchip Technology Inc.
TBLPTR = 000FFF
Results: All table writes disabled to Blockn whenever WRTn = 0.
Register Values
PROGRAM MEMORY
CODE PROTECTION
PC = 001FFE
PC = 004FFE
TABLE WRITE (WRTn) DISALLOWED
Program Memory
TBLWT *
TBLWT *
Note:
000000h
0001FFh
005FFFh
006000h
000200h
001FFFh
002000h
003FFFh
004000h
007FFFh
Code protection bits may only be written to
a ‘0’ from a ‘1’ state. It is not possible to
write a ‘1’ to a bit in the ‘0’ state. Code
protection bits are only set to ‘1’ by a full
chip erase or block erase function. The full
chip erase and block erase functions can
only be initiated via ICSP or an external
programmer.
Configuration Bit Settings
WRTB, EBTRB = 11
WRT0, EBTR0 = 01
WRT1, EBTR1 = 11
WRT2, EBTR2 = 11
WRT3, EBTR3 = 11
PIC18FXX8
DS41159D-page 277
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