PIC18F4580-I/P Microchip Technology Inc., PIC18F4580-I/P Datasheet - Page 122
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PIC18F4580-I/P
Manufacturer Part Number
PIC18F4580-I/P
Description
40 PIN, 32 KB FLASH, 1536 RAM, 36 I/O
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F4580-IP.pdf
(402 pages)
Specifications of PIC18F4580-I/P
A/d Inputs
11-Channel, 10-Bit
Comparators
2
Cpu Speed
10 MIPS
Eeprom Memory
256 Bytes
Input Output
36
Interface
CAN/I2C/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
40-pin PDIP
Programmable Memory
32K Bytes
Ram Size
1.5K Bytes
Speed
40 MHz
Timers
1-8 bit, 3-16 bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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14.1
Timer3 can operate in one of these modes:
• As a timer
• As a synchronous counter
• As an asynchronous counter
The operating mode is determined by the clock select
bit, TMR3CS (T3CON register).
FIGURE 14-1:
FIGURE 14-2:
DS41159D-page 120
PIC18FXX8
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
TMR3IF Overflow
Interrupt Flag
bit
T1OSO/
T1OSI
T1CKI
Timer3 Operation
Data Bus<7:0>
T1OSO/
Write TMR3L
Read TMR3L
T1OSI
T1CKI
TMR3IF
Overflow
Interrupt
Flag bit
TIMER3 BLOCK DIAGRAM
TIMER3 BLOCK DIAGRAM CONFIGURED IN 16-BIT READ/WRITE MODE
T1OSC
8
TMR3H
TMR3H
T1OSC
TMR3H
8
To Timer1 Clock Input
Enable
Oscillator
T1OSCEN
8
TMR3
TMR3L
Oscillator
Enable
T1OSCEN
(1)
8
TMR3L
CLR
(1)
Clock
Internal
F
CLR
OSC
/4
TMR3ON
On/Off
Clock
Internal
F
OSC
TMR3CS
When TMR3CS = 0, Timer3 increments every instruc-
tion cycle. When TMR3CS = 1, Timer3 increments on
every rising edge of the Timer1 external clock input or
the Timer1 oscillator, if enabled.
When the Timer1 oscillator is enabled (T1OSCEN is set),
the RC1/T1OSI and RC0/T1OSO/T1CKI pins become
inputs. That is, the TRISC<1:0> value is ignored.
Timer3 also has an internal “Reset input”. This Reset
can be generated by the CCP module (Section 15.1
“CCP1 Module”).
1
0
/4
TMR3ON
T3CCPx
CCP Special Trigger
On/Off
TMR3CS
T3CKPS1:T3CKPS0
1
0
T3SYNC
T3CCPx
Prescaler
CCP Special Trigger
1, 2, 4, 8
T3CKPS1:T3CKPS0
0
1
T3SYNC
2
Prescaler
1, 2, 4, 8
0
1
2004 Microchip Technology Inc.
2
Synchronized
Clock Input
Synchronize
Sleep Input
Synchronized
det
Clock Input
Synchronize
Sleep Input
det
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