PIC18F4580-I/P Microchip Technology Inc., PIC18F4580-I/P Datasheet - Page 295

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PIC18F4580-I/P

Manufacturer Part Number
PIC18F4580-I/P
Description
40 PIN, 32 KB FLASH, 1536 RAM, 36 I/O
Manufacturer
Microchip Technology Inc.
Datasheet

Specifications of PIC18F4580-I/P

A/d Inputs
11-Channel, 10-Bit
Comparators
2
Cpu Speed
10 MIPS
Eeprom Memory
256 Bytes
Input Output
36
Interface
CAN/I2C/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
40-pin PDIP
Programmable Memory
32K Bytes
Ram Size
1.5K Bytes
Speed
40 MHz
Timers
1-8 bit, 3-16 bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part Electrostatic Device

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0
BRA
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
 2004 Microchip Technology Inc.
Q Cycle Activity:
Before Instruction
After Instruction
operation
Decode
No
PC
PC
Q1
Read literal
operation
(PC) + 2 + 2n
Unconditional Branch
[ label ] BRA
-1024
None
Add the 2’s complement number ‘2n’ to
the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is a
two-cycle instruction.
1
2
HERE
1101
No
‘n’
Q2
=
=
n
address (HERE)
address (Jump)
1023
0nnn
BRA
operation
Process
n
Data
No
PC
Q3
Jump
nnnn
Write to PC
operation
No
Q4
nnnn
BSF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
FLAG_REG
FLAG_REG
Q1
register ‘f’
Bit Set f
[ label ] BSF
0
0
a
1
None
Bit ‘b’ in register ‘f’ is set. If ‘a’ is ‘0’, the
Access Bank will be selected,
overriding the BSR value. If ‘a’ = 1, then
the bank will be selected as per the
BSR value.
1
1
BSF
Read
1000
Q2
f
b
[0,1]
=
=
f<b>
255
PIC18FXX8
7
0x0A
0x8A
FLAG_REG, 7
bbba
Process
f,b[,a]
Data
Q3
DS41159D-page 293
ffff
register ‘f’
Write
Q4
ffff

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