PIC18F4580-I/P Microchip Technology Inc., PIC18F4580-I/P Datasheet - Page 317
![no-image](/images/manufacturer_photos/0/4/440/microchip_technology_inc__sml.jpg)
PIC18F4580-I/P
Manufacturer Part Number
PIC18F4580-I/P
Description
40 PIN, 32 KB FLASH, 1536 RAM, 36 I/O
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F4580-IP.pdf
(402 pages)
Specifications of PIC18F4580-I/P
A/d Inputs
11-Channel, 10-Bit
Comparators
2
Cpu Speed
10 MIPS
Eeprom Memory
256 Bytes
Input Output
36
Interface
CAN/I2C/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
40-pin PDIP
Programmable Memory
32K Bytes
Ram Size
1.5K Bytes
Speed
40 MHz
Timers
1-8 bit, 3-16 bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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RRNCF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example 1:
Example 2:
2004 Microchip Technology Inc.
Q Cycle Activity:
Before Instruction
After Instruction
Before Instruction
After Instruction
Decode
REG
REG
W
REG
W
REG
Q1
=
=
=
=
=
=
register ‘f’
Rotate Right f (no carry)
[ label ]
0
d
a
(f<n>)
(f<0>)
N, Z
The contents of register ‘f’ are rotated
one bit to the right. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default). If ‘a’
is ‘0’, the Access Bank will be selected,
overriding the BSR value. If ‘a’ is ‘1’,
then the bank will be selected as per
the BSR value (default).
1
1
RRNCF
RRNCF
Read
0100
Q2
f
[0,1]
[0,1]
1101 0111
1110 1011
?
1101 0111
1110 1011
1101 0111
255
dest<n – 1>,
dest<7>
RRNCF
REG, 1, 0
REG, W
00da
Process
Data
Q3
register f
f [,d [,a]]
ffff
destination
Write to
Q4
ffff
SETF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
REG
REG
Q1
register ‘f’
Set f
[ label ] SETF
0
a
FFh
None
The contents of the specified register
are set to FFh. If ‘a’ is ‘0’, the Access
Bank will be selected, overriding the
BSR value. If ‘a’ is ‘1’, then the bank will
be selected as per the BSR value
(default).
1
1
SETF
Read
0110
Q2
f
[0,1]
=
=
255
PIC18FXX8
f
0x5A
0xFF
REG
100a
Process
Data
f [,a]
Q3
DS41159D-page 315
ffff
register ‘f’
Write
Q4
ffff
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