PIC18F4580-I/P Microchip Technology Inc., PIC18F4580-I/P Datasheet - Page 73

• Manufacturer Part Number: PIC18F4580-I/P
• Description: 40 PIN, 32 KB FLASH, 1536 RAM, 36 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F4580-I/P

• A/d Inputs: 11-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 36
• Interface: CAN/I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 32K Bytes
• Ram Size: 1.5K Bytes
• Speed: 40 MHz
• Timers: 1-8 bit, 3-16 bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

6.5
The minimum programming block is 4 words or 8 bytes.
Word or byte programming is not supported.
Table writes are used internally to load the holding
registers needed to program the Flash memory. There
are 8 holding registers used by the table writes for
programming.
Since the Table Latch (TABLAT) is only a single byte,
the TBLWT instruction has to be executed 8 times for
each programming operation. All of the table write
operations will essentially be short writes, because only
the holding registers are written. At the end of updating
8 registers, the EECON1 register must be written to, to
start the programming operation with a long write.
The long write is necessary for programming the inter-
nal Flash. Instruction execution is halted while in a long
write cycle. The long write will be terminated by the
internal programming timer.
The EEPROM on-chip timer controls the write time.
The write/erase voltages are generated by an on-chip
charge pump rated to operate over the voltage range of
the device for byte or word operations.
FIGURE 6-5:
 2004 Microchip Technology Inc.
TBLPTR = xxxxx0
Writing to Flash Program Memory
Holding Register
8
TABLE WRITES TO FLASH PROGRAM MEMORY
TBLPTR = xxxxx1
Holding Register
8
Program Memory
TBLPTR = xxxxx2
Write Register
TABLAT
6.5.1
The sequence of events for programming an internal
program memory location should be:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Write AAh to EECON2.
11. Set the WR bit. This will begin the write cycle.
12. The CPU will stall for duration of the write (about
13. Re-enable interrupts.
14. Repeat steps 6-14 seven times to write
15. Verify the memory (table read).
This procedure will require about 18 ms to update one
row of 64 bytes of memory. An example of the required
code is given in Example 6-3.
Note:
Holding Register
Read 64 bytes into RAM.
Update data values in RAM as necessary.
Load Table Pointer with address being erased.
Do the row erase procedure.
Load Table Pointer with address of first byte
being written.
Write the first 8 bytes into the holding registers
using the TBLWT instruction, auto-increment
may be used.
Set the EECON1 register for the write operation:
• set the EEPGD bit to point to program memory;
• clear the CFGS bit to access program memory;
• set the WREN to enable byte writes.
Disable interrupts.
Write 55h to EECON2.
2 ms using internal timer).
64 bytes.
8
FLASH PROGRAM MEMORY WRITE
SEQUENCE
Before setting the WR bit, the Table
Pointer address needs to be within the
intended address range of the 8 bytes in
the holding registers.
TBLPTR = xxxxx7
PIC18FXX8
Holding Register
DS41159D-page 71
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