PIC18F4580-I/P Microchip Technology Inc., PIC18F4580-I/P Datasheet - Page 290
![no-image](/images/manufacturer_photos/0/4/440/microchip_technology_inc__sml.jpg)
PIC18F4580-I/P
Manufacturer Part Number
PIC18F4580-I/P
Description
40 PIN, 32 KB FLASH, 1536 RAM, 36 I/O
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F4580-IP.pdf
(402 pages)
Specifications of PIC18F4580-I/P
A/d Inputs
11-Channel, 10-Bit
Comparators
2
Cpu Speed
10 MIPS
Eeprom Memory
256 Bytes
Input Output
36
Interface
CAN/I2C/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
40-pin PDIP
Programmable Memory
32K Bytes
Ram Size
1.5K Bytes
Speed
40 MHz
Timers
1-8 bit, 3-16 bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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ADDWFC
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
DS41159D-page 288
PIC18FXX8
Q Cycle Activity:
Before Instruction
After Instruction
Decode
Carry bit =
REG
W
Carry bit =
REG
W
Q1
ADD W and Carry bit to f
[ label ] ADDWFC
0
d
a
(W) + (f) + (C)
N, OV, C, DC, Z
Add W, the Carry flag and data memory
location ‘f’. If ‘d’ is ‘0’, the result is placed
in W. If ‘d’ is ‘1’, the result is placed in
data memory location ‘f’. If ‘a’ is ‘0’, the
Access Bank will be selected. If ‘a’ is ‘1’,
the BSR will not be overridden.
1
1
=
=
=
=
register ‘f’
ADDWFC
Read
0010
f
[0,1]
[0,1]
Q2
1
0x02
0x4D
0
0x02
0x50
255
00da
REG, W
Process
Data
dest
Q3
f [,d [,a]]
ffff
destination
Write to
Q4
ffff
ANDLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
W
W
Q1
Read literal
=
=
AND Literal with W
[ label ] ANDLW
0
(W) .AND. k
N, Z
The contents of W are ANDed with the
8-bit literal ‘k’. The result is placed in W.
1
1
ANDLW
0000
Q2
‘k’
k
0xA3
0x03
2004 Microchip Technology Inc.
255
1011
0x5F
Process
W
Data
Q3
k
kkkk
Write to W
Q4
kkkk
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