PIC18F4580-I/P Microchip Technology Inc., PIC18F4580-I/P Datasheet - Page 116

• Manufacturer Part Number: PIC18F4580-I/P
• Description: 40 PIN, 32 KB FLASH, 1536 RAM, 36 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F4580-I/P

• A/d Inputs: 11-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 36
• Interface: CAN/I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 32K Bytes
• Ram Size: 1.5K Bytes
• Speed: 40 MHz
• Timers: 1-8 bit, 3-16 bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

12.1
Timer1 can operate in one of these modes:
• As a timer
• As a synchronous counter
• As an asynchronous counter
The operating mode is determined by the clock select
bit, TMR1CS (T1CON register).
FIGURE 12-1:
FIGURE 12-2:
DS41159D-page 114
PIC18FXX8
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This reduces power drain.
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This reduces power drain.
T1CKI/T1OSO
Timer1 Operation
T1CKI/T1OSO
TMR1IF
Overflow
Interrupt
Flag bit
Data Bus<7:0>
TMR1IF
Overflow
Interrupt
Flag bit
Write TMR1L
Read TMR1L
T1OSI
T1OSI
TIMER1 BLOCK DIAGRAM
TIMER1 BLOCK DIAGRAM: 16-BIT READ/WRITE MODE
8
T1OSC
T1OSC
High Byte
TMR1H
TMR1H
8
Timer 1
8
TMR1
TMR1
Oscillator
T1OSCEN
Enable
Oscillator
Enable
T1OSCEN
TMR1L
TMR1L
8
CLR
(1)
(1)
Internal
Clock
F
OSC
Clock
/4
Internal
F
TMR1ON
CCP Special Event Trigger
OSC
On/Off
TMR1CS
When TMR1CS is clear, Timer1 increments every
instruction cycle. When TMR1CS is set, Timer1
increments on every rising edge of the external clock
input or the Timer1 oscillator, if enabled.
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RC1/T1OSI and RC0/T1OSO/T1CKI pins
become inputs. That is, the TRISC<1:0> value is
ignored.
Timer1 also has an internal “Reset input”. This Reset
can be generated by the CCP module (Section 15.1
“CCP1 Module”).
/4
TMR1ON
Special Event Trigger
1
0
On/Off
TMR1CS
T1CKPS1:T1CKPS0
1
0
T1SYNC
Prescaler
1, 2, 4, 8
T1CKPS1:T1CKPS0
0
1
T1SYNC
Prescaler
1, 2, 4, 8
2
0
1
2
 2004 Microchip Technology Inc.
Synchronized
Clock Input
Synchronize
Sleep Input
Synchronized
Clock Input
Synchronize
Sleep Input
det
det