PIC18F4580-I/P Microchip Technology Inc., PIC18F4580-I/P Datasheet - Page 25

• Manufacturer Part Number: PIC18F4580-I/P
• Description: 40 PIN, 32 KB FLASH, 1536 RAM, 36 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F4580-I/P

• A/d Inputs: 11-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 36
• Interface: CAN/I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 32K Bytes
• Ram Size: 1.5K Bytes
• Speed: 40 MHz
• Timers: 1-8 bit, 3-16 bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

2.7
When the device executes a SLEEP instruction, the
on-chip clocks and oscillator are turned off and the
device is held at the beginning of an instruction cycle
(Q1 state). With the oscillator off, the OSC1 and OSC2
signals will stop oscillating. Since all the transistor
switching currents have been removed, Sleep mode
achieves the lowest current consumption of the device
(only leakage currents). Enabling any on-chip feature
that will operate during Sleep will increase the current
consumed during Sleep. The user can wake from
Sleep through external Reset, Watchdog Timer Reset
or through an interrupt.
2.8
Power-up delays are controlled by two timers so that no
external Reset circuitry is required for most applica-
tions. The delays ensure that the device is kept in
TABLE 2-3:
 2004 Microchip Technology Inc.
RC
RCIO
ECIO
EC
LP, XT and HS
Note:
OSC Mode
Effects of Sleep Mode on the
On-Chip Oscillator
Power-up Delays
See Table 3-1 in Section 3.0 “Reset” for time-outs due to Sleep and MCLR Reset.
OSC1 AND OSC2 PIN STATES IN SLEEP MODE
Floating, external resistor should pull high
Floating, external resistor should pull high
Floating
Floating
Feedback inverter disabled at quiescent
voltage level
OSC1 Pin
Reset until the device power supply and clock are
stable. For additional information on Reset operation,
see Section 3.0 “Reset”.
The first timer is the Power-up Timer (PWRT), which
optionally provides a fixed delay of T
#D033) on power-up only (POR and BOR). The second
timer is the Oscillator Start-up Timer (OST), intended to
keep the chip in Reset until the crystal oscillator is
stable.
With the PLL enabled (HS4 Oscillator mode), the time-
out sequence following a Power-on Reset is different
from other oscillator modes. The time-out sequence is
as follows: the PWRT time-out is invoked after a POR
time delay has expired, then the Oscillator Start-up
Timer (OST) is invoked. However, this is still not a
sufficient amount of time to allow the PLL to lock at high
frequencies. The PWRT timer is used to provide an
additional fixed 2 ms (nominal) to allow the PLL ample
time to lock to the incoming clock frequency.
At logic low
Configured as PORTA, bit 6
Configured as PORTA, bit 6
At logic low
Feedback inverter disabled at quiescent
voltage level
PIC18FXX8
OSC2 Pin
DS41159D-page 23
PWRT
(parameter