PIC18F4580-I/P Microchip Technology Inc., PIC18F4580-I/P Datasheet - Page 104

• Manufacturer Part Number: PIC18F4580-I/P
• Description: 40 PIN, 32 KB FLASH, 1536 RAM, 36 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F4580-I/P

• A/d Inputs: 11-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 36
• Interface: CAN/I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 32K Bytes
• Ram Size: 1.5K Bytes
• Speed: 40 MHz
• Timers: 1-8 bit, 3-16 bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

9.4
PORTD is an 8-bit wide, bidirectional port. The corre-
sponding Data Direction register for the port is TRISD.
Setting a TRISD bit (= 1) will make the corresponding
PORTD pin an input (i.e., put the corresponding output
driver in a high-impedance mode). Clearing a TRISD
bit (= 0) will make the corresponding PORTD pin an
output (i.e., put the contents of the output latch on the
selected pin).
Read-modify-write operations on the LATD register
read and write the latched output value for PORTD.
PORTD uses Schmitt Trigger input buffers. Each pin is
individually configurable as an input or output.
FIGURE 9-9:
DS41159D-page 102
PIC18FXX8
Note:
PORTD, TRISD and LATD
Registers
This port is only available on the
PIC18F448 and PIC18F458.
Note 1: I/O pins have diode protection to V
PORT/PSP Select
PSP Data Out
RD LATD
Data Bus
WR LATD
or
PORTD
RD TRISD
PSP Read
RD PORTD
PSP Write
C1IN+
WR TRISD
PORTD BLOCK DIAGRAM IN I/O PORT MODE
Data Latch
TRIS Latch
D
D
CK
CK
Q
Q
Q
Q
DD
and V
Q
PORTD can be configured as an 8-bit wide, micro-
processor port (Parallel Slave Port or PSP) by setting
the control bit PSPMODE (TRISE<4>). In this mode,
the input buffers are TTL. See Section 10.0 “Parallel
Slave Port” for additional information.
PORTD is also multiplexed with the analog comparator
module and the ECCP module.
EXAMPLE 9-4:
CLRF
CLRF
MOVLW
MOVWF
MOVLW
MOVWF
SS
.
EN
D
PORTD
LATD
07h
CMCON
0CFh
TRISD
Schmitt
Trigger
V
N
Vss
P
DD
INITIALIZING PORTD
; Initialize PORTD by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; comparator off
; Value used to
; initialize data
; direction
; Set RD3:RD0 as inputs
; RD5:RD4 as outputs
; RD7:RD6 as inputs
 2004 Microchip Technology Inc.
C1IN+ pin
RD0/PSP0/
(1)