PIC18F4580-I/P Microchip Technology Inc., PIC18F4580-I/P Datasheet - Page 244

• Manufacturer Part Number: PIC18F4580-I/P
• Description: 40 PIN, 32 KB FLASH, 1536 RAM, 36 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F4580-I/P

• A/d Inputs: 11-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 36
• Interface: CAN/I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 32K Bytes
• Ram Size: 1.5K Bytes
• Speed: 40 MHz
• Timers: 1-8 bit, 3-16 bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

REGISTER 20-2:
DS41159D-page 242
PIC18FXX8
bit 7
bit 6
bit 5-4
bit 3-0
ADFM: A/D Result Format Select bit
1 = Right justified. Six (6) Most Significant bits of ADRESH are read as ‘0’.
0 = Left justified. Six (6) Least Significant bits of ADRESL are read as ‘0’.
ADCS2: A/D Conversion Clock Select bit (ADCON1 bits in bold)
Unimplemented: Read as ‘0’
PCFG3:PCFG0: A/D Port Configuration Control bits
Legend:
R = Readable bit
-n = Value at POR
bit 7
ADCON1: A/D CONTROL REGISTER 1
A = Analog input D = Digital I/O
C/R = # of analog input channels/# of A/D voltage references
Note:
PCFG
<ADCS2>
0000
0001
0010
0011
0100
0101
011x
1000
1001
1010
1011
1100
1101
1110
1111
ADFM
R/W-0
ADCON1
Note:
0
0
0
0
1
1
1
1
AN7
On any device Reset, the port pins that are multiplexed with analog functions (ANx)
are forced to be analog inputs.
Shaded cells indicate channels available only on PIC18F4X8 devices.
D
D
D
D
D
D
D
D
D
D
D
D
A
A
A
ADCS2
R/W-0
<ADCS1:ADCS0>
AN6
A
A
D
D
D
D
D
A
D
D
D
D
D
D
D
ADCON0
00
01
10
11
00
01
10
11
AN5
A
A
D
D
D
D
D
A
A
A
A
D
D
D
D
W = Writable bit
‘1’ = Bit is set
U-0
—
AN4
D
D
D
D
D
D
A
A
A
A
A
A
A
A
A
F
F
F
F
F
F
F
F
OSC
OSC
OSC
RC
OSC
OSC
OSC
RC
V
V
V
V
V
V
V
V
V
U-0
(clock derived from the internal A/D RC oscillator)
(clock derived from the internal A/D RC oscillator)
AN3
—
REF
REF
REF
REF
REF
REF
REF
REF
REF
/2
/8
/32
/4
/16
/64
A
A
A
D
A
D
+
+
+
+
+
+
+
+
+
V
V
V
V
V
AN2
REF
REF
REF
REF
REF
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
A
A
A
A
D
D
D
A
A
D
PCFG3
R/W-0
-
-
-
-
-
Clock Conversion
AN1
A
A
A
A
A
A
D
A
A
A
A
A
A
D
D
PCFG2
R/W-0
AN0
D
A
A
A
A
A
A
A
A
A
A
A
A
A
A
 2004 Microchip Technology Inc.
V
AN3
AN3
AN3
AN3
AN3
AN3
AN3
AN3
AN3
V
V
V
V
V
REF
—
x = Bit is unknown
DD
DD
DD
DD
DD
PCFG1
R/W-0
+
V
AN2
AN2
AN2
AN2
AN2
V
V
V
V
V
V
V
V
V
REF
—
SS
SS
SS
SS
SS
SS
SS
SS
SS
-
PCFG0
R/W-0
C/R
8/0
7/1
5/0
4/1
3/0
2/1
0/0
6/2
6/0
5/1
4/2
3/2
2/2
1/0
1/2
bit 0