PIC18F4580-I/P Microchip Technology Inc., PIC18F4580-I/P Datasheet - Page 241

• Manufacturer Part Number: PIC18F4580-I/P
• Description: 40 PIN, 32 KB FLASH, 1536 RAM, 36 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F4580-I/P

• A/d Inputs: 11-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 36
• Interface: CAN/I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 32K Bytes
• Ram Size: 1.5K Bytes
• Speed: 40 MHz
• Timers: 1-8 bit, 3-16 bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

TABLE 19-3:
19.13.4
When an error occurs during transmission or reception
of a message, the message error flag IRXIF will be set
and if the IRXIE bit is set, an interrupt will be generated.
This is intended to be used to facilitate baud rate
determination when used in conjunction with Listen
Only mode.
19.13.5
When the PIC18FXX8 is in Sleep mode and the bus
activity wake-up interrupt is enabled, an interrupt will be
generated and the WAKIF bit will be set when activity is
detected on the CAN bus. This interrupt causes the
PIC18FXX8 to exit Sleep mode. The interrupt is reset
by the MCU, clearing the WAKIF bit.
 2004 Microchip Technology Inc.
Key:
ERR = ERRIF * ERRIE
TX0 = TXB0IF * TXB0IE RX1 = RXB1IF * RXB1IE
TX1 = TXB1IF * TXB1IE WAK = WAKIF * WAKIE
TX2 = TXB2IF * TXB2IE
<2:0>
ICOD
000
001
010
011
100
101
110
111
Interrupt
Wake on
Interrupt
TXB2
TXB1
TXB0
RXB1
RXB0
MESSAGE ERROR INTERRUPT
BUS ACTIVITY WAKE-UP
INTERRUPT
None
Error
VALUES FOR ICODE<2:0>
ERR•WAK•TX0•TX1•TX2•RX0•
RX1
ERR
ERR•TX0•TX1•TX2
ERR•TX0•TX1
ERR•TX0
ERR•TX0•TX1•TX2•RX0•RX1
ERR•TX0•TX1•TX2•RX0
ERR•TX0•TX1•TX2•RX0•RX1•
WAK
Boolean Expression
RX0 = RXB0IF * RXB0IE
19.13.6
When the error interrupt is enabled, an interrupt is
generated if an overflow condition occurs or if the error
state of transmitter or receiver has changed. The error
flags in COMSTAT will indicate one of the following
conditions.
19.13.6.1
An overflow condition occurs when the MAB has
assembled a valid received message (the message
meets the criteria of the acceptance filters) and the
receive buffer associated with the filter is not available
for loading of a new message. The associated
COMSTAT.RXnOVFL bit will be set to indicate the
overflow condition. This bit must be cleared by the
MCU.
19.13.6.2
The receive error counter has reached the MCU
warning limit of 96.
19.13.6.3
The transmit error counter has reached the MCU
warning limit of 96.
19.13.6.4
The receive error counter has exceeded the error-
passive limit of 127 and the device has gone to
error-passive state.
19.13.6.5
The transmit error counter has exceeded the error-
passive limit of 127 and the device has gone to
error-passive state.
19.13.6.6
The transmit error counter has exceeded 255 and the
device has gone to bus-off state.
19.13.7
Interrupts are directly associated with one or more
status flags in the PIR register. Interrupts are pending
as long as one of the flags is set. Once an interrupt flag
is set by the device, the flag cannot be reset by the
microcontroller until the interrupt condition is removed.
ERROR INTERRUPT
INTERRUPT ACKNOWLEDGE
Receiver Overflow
Receiver Warning
Transmitter Warning
Receiver Bus Passive
Transmitter Bus Passive
Bus-Off
PIC18FXX8
DS41159D-page 239