PIC18F4580-I/P Microchip Technology Inc., PIC18F4580-I/P Datasheet - Page 109

• Manufacturer Part Number: PIC18F4580-I/P
• Description: 40 PIN, 32 KB FLASH, 1536 RAM, 36 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F4580-I/P

• A/d Inputs: 11-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 36
• Interface: CAN/I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 32K Bytes
• Ram Size: 1.5K Bytes
• Speed: 40 MHz
• Timers: 1-8 bit, 3-16 bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

10.0
In addition to its function as a general I/O port, PORTD
can also operate as an 8-bit wide Parallel Slave Port
(PSP) or microprocessor port. PSP operation is
controlled by the 4 upper bits of the TRISE register
(Register 9-1).
(TRISE<4>) enables PSP operation. In Slave mode,
the port is asynchronously readable and writable by the
external world.
The PSP can directly interface to an 8-bit micro-
processor data bus. The external microprocessor can
read or write the PORTD latch as an 8-bit latch. Setting
the control bit PSPMODE enables the PORTE I/O pins
to become control inputs for the microprocessor port.
When set, port pin RE0 is the RD input, RE1 is the WR
input and RE2 is the CS (chip select) input. For this
functionality, the corresponding data direction bits of
the TRISE register (TRISE<2:0>) must be configured
as inputs (set).
A write to the PSP occurs when both the CS and WR
lines are first detected low. A read from the PSP occurs
when both the CS and RD lines are first detected low.
The timing for the control signals in Write and Read
modes is shown in Figure 10-2 and Figure 10-3,
respectively.
FIGURE 10-2:
 2004 Microchip Technology Inc.
Note:
PORTD
PSPIF
PARALLEL SLAVE PORT
OBF
CS
WR
RD
IBF
The Parallel Slave Port is only available on
PIC18F4X8 devices.
Setting
Q1
PARALLEL SLAVE PORT WRITE WAVEFORMS
control
Q2
Q3
bit
PSPMODE
Q4
Q1
Q2
FIGURE 10-1:
Q3
Note:
Data Bus
Set Interrupt Flag
PSPIF (PIR1<7>)
WR LATD
or
WR PORTD
RD PORTD
RD LATD
I/O pins have diode protection to V
Q4
Data Latch
Q
D
One bit of PORTD
CK
Q1
EN
PORTD AND PORTE
BLOCK DIAGRAM
(PARALLEL SLAVE PORT)
EN
Q
D
PIC18FXX8
Q2
Chip Select
Read
Write
Q3
DS41159D-page 107
TTL
DD
TTL
TTL
TTL
and V
PORTE pins
Q4
SS
RDx pin
.
CS
WR
RD