PIC18F4580-I/P Microchip Technology Inc., PIC18F4580-I/P Datasheet - Page 298

• Manufacturer Part Number: PIC18F4580-I/P
• Description: 40 PIN, 32 KB FLASH, 1536 RAM, 36 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F4580-I/P

• A/d Inputs: 11-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 36
• Interface: CAN/I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 32K Bytes
• Ram Size: 1.5K Bytes
• Speed: 40 MHz
• Timers: 1-8 bit, 3-16 bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

BZ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
DS41159D-page 296
PIC18FXX8
Q Cycle Activity:
If Jump:
If No Jump:
Before Instruction
After Instruction
operation
Decode
Decode
PC
If Zero
If Zero
No
Q1
Q1
PC
PC
Read literal
Read literal
operation
Branch if Zero
[ label ] BZ
-128
if Zero bit is ‘1’
(PC) + 2 + 2n
None
If the Zero bit is ‘1’, then the program
will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next instruc-
tion, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
1
1(2)
HERE
1110
No
Q2
‘n’
Q2
‘n’
=
=
=
=
=
n
address (HERE)
1;
address (Jump)
0;
address (HERE + 2)
127
0000
operation
n
BZ
Process
Process
Data
Data
No
PC
Q3
Q3
Jump
nnnn
operation
operation
Write to
PC
No
No
Q4
Q4
nnnn
CALL
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
1st word (k<7:0>)
2nd word(k<19:8>)
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
operation
Decode
No
PC
PC
TOS
WS
BSRS
STATUSS=
Q1
Read literal
=
=
=
=
=
operation
Subroutine Call
[ label ] CALL k [,s]
0
s
(PC) + 4
k
if s = 1
(W)
(Status)
(BSR)
None
Subroutine call of entire 2-Mbyte
memory range. First, return address
(PC + 4) is pushed onto the return
stack. If ‘s’ = 1, the W, Status and BSR
registers are also pushed into their
respective shadow registers, WS,
STATUSS and BSRS. If ‘s’ = 0, no
update occurs (default). Then, the
20-bit value ‘k’ is loaded into PC<20:1>.
CALL is a two-cycle instruction.
2
2
‘k’<7:0>,
HERE
1110
1111
No
Q2
k
[0,1]
address (HERE)
address (THERE)
address (HERE + 4)
W
BSR
Status
PC<20:1>,
 2004 Microchip Technology Inc.
WS,
1048575
BSRS
STATUSS,
k
TOS,
110s
19
Push PC to
CALL
operation
kkk
stack
No
Q3
k
THERE,FAST
kkkk
7
kkk
Write to PC
Read literal
‘k’<19:8>,
operation
No
Q4
kkkk
kkkk
0
8