PIC18F4580-I/P Microchip Technology Inc., PIC18F4580-I/P Datasheet - Page 121

• Manufacturer Part Number: PIC18F4580-I/P
• Description: 40 PIN, 32 KB FLASH, 1536 RAM, 36 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F4580-I/P

• A/d Inputs: 11-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 36
• Interface: CAN/I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 32K Bytes
• Ram Size: 1.5K Bytes
• Speed: 40 MHz
• Timers: 1-8 bit, 3-16 bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

14.0
The Timer3 module timer/counter has the following
features:
• 16-bit timer/counter
• Readable and writable (both registers)
• Internal or external clock select
• Interrupt-on-overflow from FFFFh to 0000h
• Reset from CCP1/ECCP1 module trigger
REGISTER 14-1:
 2004 Microchip Technology Inc.
(two 8-bit registers: TMR3H and TMR3L)
TIMER3 MODULE
bit 7
bit 6,3
bit 5-4
bit 2
bit 1
bit 0
T3CON:TIMER3 CONTROL REGISTER
RD16: 16-bit Read/Write Mode Enable bit
1 = Enables register read/write of Timer3 in one 16-bit operation
0 = Enables register read/write of Timer3 in two 8-bit operations
T3ECCP1:T3CCP1: Timer3 and Timer1 to CCP1/ECCP1 Enable bits
1x = Timer3 is the clock source for compare/capture CCP1 and ECCP1 modules
01 = Timer3 is the clock source for compare/capture of ECCP1,
00 = Timer1 is the clock source for compare/capture CCP1 and ECCP1 modules
T3CKPS1:T3CKPS0: Timer3 Input Clock Prescale Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value
T3SYNC: Timer3 External Clock Input Synchronization Control bit
(Not usable if the system clock comes from Timer1/Timer3.)
When TMR3CS = 1:
1 = Do not synchronize external clock input
0 = Synchronize external clock input
When TMR3CS = 0:
This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0.
TMR3CS: Timer3 Clock Source Select bit
1 = External clock input from Timer1 oscillator or T1CKI (on the rising edge after the first falling edge)
0 = Internal clock (F
TMR3ON: Timer3 On bit
1 = Enables Timer3
0 = Stops Timer3
Legend:
R = Readable bit
-n = Value at POR
bit 7
R/W-0
RD16
Timer1 is the clock source for compare/capture of CCP1
T3ECCP1 T3CKPS1 T3CKPS0
R/W-0
OSC
/4)
R/W-0
W = Writable bit
‘1’ = Bit is set
R/W-0
Figure 14-1 is a simplified block diagram of the Timer3
module.
Register 14-1 shows the Timer3 Control register. This
register controls the operating mode of the Timer3
module and sets the CCP1 and ECCP1 clock source.
Register 12-1 shows the Timer1 Control register. This
register controls the operating mode of the Timer1
module, as well as contains the Timer1 Oscillator
Enable bit (T1OSCEN) which can be a clock source for
Timer3.
Note:
T3CCP1
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
Timer3 is disabled on POR.
T3SYNC
R/W-0
PIC18FXX8
x = Bit is unknown
TMR3CS
R/W-0
DS41159D-page 119
TMR3ON
R/W-0
bit 0