PIC18F4580-I/P Microchip Technology Inc., PIC18F4580-I/P Datasheet - Page 102

• Manufacturer Part Number: PIC18F4580-I/P
• Description: 40 PIN, 32 KB FLASH, 1536 RAM, 36 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F4580-I/P

• A/d Inputs: 11-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 36
• Interface: CAN/I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 32K Bytes
• Ram Size: 1.5K Bytes
• Speed: 40 MHz
• Timers: 1-8 bit, 3-16 bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

9.3
PORTC is an 8-bit wide, bidirectional port. The corre-
sponding Data Direction register is TRISC. Setting a
TRISC bit (= 1) will make the corresponding PORTC
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISC bit (= 0)
will make the corresponding PORTC pin an output (i.e.,
put the contents of the output latch on the selected pin).
Read-modify-write operations on the LATC register,
read and write the latched output value for PORTC.
PORTC is multiplexed with several peripheral functions
(Table 9-5). PORTC pins have Schmitt Trigger input
buffers.
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bit to make a pin an output,
FIGURE 9-8:
DS41159D-page 100
PIC18FXX8
RD LATC
Data Bus
WR TRISC
RD TRISC
Peripheral Enable
Note 1: I/O pins have diode protection to V
Peripheral Out Select
Peripheral Data Out
WR LATC
or
WR PORTC
RD PORTC
Peripheral Data In
PORTC, TRISC and LATC
Registers
PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE)
TRIS Latch
Data Latch
D
D
CK
CK
Q
Q
Q
Q
DD
Override
TRIS
0
1
and V
Q
SS
.
EN
D
while other peripherals override the TRIS bit to make a
pin an input. The user should refer to the corresponding
peripheral section for the correct TRIS bit settings.
The pin override value is not loaded into the TRIS
register. This allows read-modify-write of the TRIS
register, without concern due to peripheral overrides.
EXAMPLE 9-3:
CLRF
CLRF
MOVLW
MOVWF
Schmitt
Trigger
V
V
N
P
SS
DD
PORTC
LATC
0CFh
TRISC
I/O pin
RC0
RC1
RC2
RC3
RC4
RC5
RC6
RC7
Pin
INITIALIZING PORTC
(1)
; Initialize PORTC by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RC3:RC0 as inputs
; RC5:RC4 as outputs
; RC7:RC6 as inputs
 2004 Microchip Technology Inc.
Override
TRIS OVERRIDE
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Timer1 Oscillator
for Timer1/Timer3
Timer1 Oscillator
for Timer1/Timer3
—
SPI™/I
Master Clock
I
SPI Data Out
USART Async
Xmit, Sync Clock
USART Sync Data
Out
2
C Data Out
Peripheral
2
C™