PIC18F4580-I/P Microchip Technology Inc., PIC18F4580-I/P Datasheet - Page 126

• Manufacturer Part Number: PIC18F4580-I/P
• Description: 40 PIN, 32 KB FLASH, 1536 RAM, 36 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F4580-I/P

• A/d Inputs: 11-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 36
• Interface: CAN/I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 32K Bytes
• Ram Size: 1.5K Bytes
• Speed: 40 MHz
• Timers: 1-8 bit, 3-16 bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

15.1
Capture/Compare/PWM Register1 (CCPR1) is com-
prised of two 8-bit registers: CCPR1L (low byte) and
CCPR1H (high byte). The CCP1CON register controls
the operation of CCP1. All are readable and writable.
Table 15-1 shows the timer resources of the CCP
module modes.
TABLE 15-1:
15.2
In Capture mode, CCPR1H:CCPR1L captures the 16-
bit value of the TMR1 or TMR3 register when an event
occurs on pin RC2/CCP1. An event is defined as:
• every falling edge
• every rising edge
• every 4th rising edge
• every 16th rising edge
TABLE 15-2:
DS41159D-page 124
PIC18FXX8
Capture
Capture
Compare
PWM
PWM
PWM
CCP1
Mode
CCP1 Mode
Compare
CCP1 Module
Capture Mode
Capture
PWM
Capture
Compare
Compare
PWM
Capture
Compare
ECCP1
CCP1 MODE – TIMER
RESOURCE
INTERACTION OF CCP1 AND ECCP1 MODULES
Mode
TMR1 or TMR3 time base. Time base can be different for each CCP.
The compare could be configured for the special event trigger which clears either TMR1
or TMR3, depending upon which time base is used.
The compare(s) could be configured for the special event trigger which clears TMR1 or
TMR3, depending upon which time base is used.
The PWMs will have the same frequency and update rate (TMR2 interrupt).
None.
None.
Timer1 or Timer3
Timer1 or Timer3
Timer Resource
Timer2
An event is selected by control bits CCP1M3:CCP1M0
(CCP1CON<3:0>). When a capture is made, the
interrupt request flag bit, CCP1IF (PIR registers), is set.
It must be cleared in software. If another capture
occurs before the value in register CCPR1 is read, the
old captured value will be lost.
15.2.1
In Capture mode, the RC2/CCP1 pin should be
configured as an input by setting the TRISC<2> bit.
15.2.2
The timers used with the capture feature (either Timer1
and/or Timer3) must be running in Timer mode or Syn-
chronized Counter mode. In Asynchronous Counter
mode, the capture operation may not work. The timer
used with each CCP module is selected in the T3CON
register.
Note:
Interaction
CCP PIN CONFIGURATION
If the RC2/CCP1 is configured as an out-
put, a write to the port can cause a capture
condition.
TIMER1/TIMER3 MODE SELECTION
 2004 Microchip Technology Inc.