PIC18F4580-I/P Microchip Technology Inc., PIC18F4580-I/P Datasheet - Page 165

• Manufacturer Part Number: PIC18F4580-I/P
• Description: 40 PIN, 32 KB FLASH, 1536 RAM, 36 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F4580-I/P

• A/d Inputs: 11-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 36
• Interface: CAN/I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 32K Bytes
• Ram Size: 1.5K Bytes
• Speed: 40 MHz
• Timers: 1-8 bit, 3-16 bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

17.4.4.5
If a user clears the CKP bit, the SCL output is forced to
‘0’. Setting the CKP bit will not assert the SCL output
low until the SCL output is already sampled low. If the
user attempts to drive SCL low, the CKP bit will not
FIGURE 17-12:
 2004 Microchip Technology Inc.
WR
SSPCON1
SDA
SCL
CKP
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Clock Synchronization and
the CKP bit
CLOCK SYNCHRONIZATION TIMING
Master device
asserts clock
DX
assert the SCL line until an external I
has already asserted the SCL line. The SCL output will
remain low until the CKP bit is set and all other devices
on the I
a write to the CKP bit will not violate the minimum high
time requirement for SCL (see Figure 17-12).
Master device
deasserts clock
2
C bus have deasserted SCL. This ensures that
PIC18FXX8
DS41159D-page 163
2
DX – 1
C master device