PIC18F4580-I/P Microchip Technology Inc., PIC18F4580-I/P Datasheet - Page 56

• Manufacturer Part Number: PIC18F4580-I/P
• Description: 40 PIN, 32 KB FLASH, 1536 RAM, 36 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F4580-I/P

• A/d Inputs: 11-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 36
• Interface: CAN/I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 32K Bytes
• Ram Size: 1.5K Bytes
• Speed: 40 MHz
• Timers: 1-8 bit, 3-16 bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

4.10
The Access Bank is an architectural enhancement that
is very useful for C compiler code optimization. The
techniques used by the C compiler are also useful for
programs written in assembly.
This data memory region can be used for:
• Intermediate computational values
• Local variables of subroutines
• Faster context saving/switching of variables
• Common variables
• Faster evaluation/control of SFRs (no banking)
The Access Bank is comprised of the upper 160 bytes
in Bank 15 (SFRs) and the lower 96 bytes in Bank 0.
These two sections will be referred to as Access Bank
High and Access Bank Low, respectively. Figure 4-6
indicates the Access Bank areas.
A bit in the instruction word specifies if the operation is
to occur in the bank specified by the BSR register or in
the Access Bank.
When forced in the Access Bank (a = 0), the last
address in Access Bank Low is followed by the first
address in Access Bank High. Access Bank High maps
most of the Special Function Registers so that these
registers can be accessed without any software
overhead.
FIGURE 4-7:
DS41159D-page 54
PIC18FXX8
Note 1: For register file map detail, see Table 4-1.
Bank Select
Access Bank
2: The access bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the
3: The MOVFF instruction embeds the entire 12-bit address in the instruction.
registers of the Access Bank.
BSR<3:0>
(2)
DIRECT ADDRESSING
Location Select
7
Direct Addressing
Data
Memory
From Opcode
(1)
(3)
(3)
000h
0FFh
Bank 0
00h
0
4.11
The need for a large general purpose memory space
dictates a RAM banking scheme. The data memory is
partitioned into sixteen banks. When using direct
addressing, the BSR should be configured for the
desired bank.
BSR<3:0> holds the upper 4 bits of the 12-bit RAM
address. The BSR<7:4> bits will always read ‘0’s and
writes will have no effect.
A MOVLB instruction has been provided in the
instruction set to assist in selecting banks.
If the currently selected bank is not implemented, any
read will return all ‘0’s and all writes are ignored. The
Status register bits will be set/cleared as appropriate for
the instruction performed.
Each Bank extends up to FFh (256 bytes). All data
memory is implemented as static RAM.
A MOVFF instruction ignores the BSR since the 12-bit
addresses are embedded into the instruction word.
Section 4.12 “Indirect Addressing, INDF and FSR
Registers” provides a description of indirect address-
ing, which allows linear addressing of the entire RAM
space.
100h
1FFh
Bank 1
01h
Bank Select Register (BSR)
 2004 Microchip Technology Inc.
0E00h
0EFFh
Bank 14
0Eh
0F00h
0FFFh
Bank 15
0Fh