HD6417750RF240DV Renesas Electronics America, HD6417750RF240DV Datasheet - Page 948

• Manufacturer Part Number: HD6417750RF240DV
• Description: MPU 3V 16K I-TEMP,PB-FREE 208-QF
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF240DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 20 User Break Controller (UBC)
value of the PCBA, DBEB, PCBB, and SEQ bits is undefined after a power-on reset or manual
reset, so these bits should be initialized by software as necessary.
Bit 15—Condition Match Flag A (CMFA): Set to 1 when a break condition set for channel A is
satisfied. This flag is not cleared to 0 (to confirm that the flag is set again after once being set, it
should be cleared with a write.)
Bit 15: CMFA
0
1
Bit 14—Condition Match Flag B (CMFB): Set to 1 when a break condition set for channel B is
satisfied. This flag is not cleared to 0 (to confirm that the flag is set again after once being set, it
should be cleared with a write.)
Bit 14: CMFB
0
1
Bits 13 to 11—Reserved: These bits are always read as 0, and should only be written with 0.
Bit 10—Instruction Access Break Select A (PCBA): Specifies whether a channel A instruction
access cycle break is to be effected before or after the instruction is executed. This bit is not
initialized by a power-on reset or manual reset.
Bit 10: PCBA
0
1
Bits 9 and 8—Reserved: These bits are always read as 0, and should only be written with 0.
Rev.7.00 Oct. 10, 2008 Page 862 of 1074
REJ09B0366-0700
Description
Channel A break condition is not matched
Channel A break condition match has occurred
Description
Channel B break condition is not matched
Channel B break condition match has occurred
Description
Channel A PC break is effected before instruction execution
Channel A PC break is effected after instruction execution
(Initial value)
(Initial value)