HD6417750RF240DV Renesas Electronics America, HD6417750RF240DV Datasheet - Page 331

• Manufacturer Part Number: HD6417750RF240DV
• Description: MPU 3V 16K I-TEMP,PB-FREE 208-QF
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF240DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

(a) Serial execution: non-parallel-executable instructions
(b) Parallel execution: parallel-executable and no dependency
(c) Issue rate: multi-step instruction
(d) Branch
SHAD R0,R1
ADD
next
ADD
MOV.L @R4,R5
AND.B#1,@(R0,GBR)
MOV
next
BT/S L_far
ADD R0,R1
SUB R2,R3
BT/S L_far
ADD R0,R1
L_far
BT L_skip
ADD #1,R0
L_skip:
R2,R3
R2,R1
R1,R2
I
I
I
I
I
I
I
I
I
I
I
I
Figure 8.3 Examples of Pipelined Execution
No stall
4 stall cycles
D
D
D
D
D
D
D
D
D
D
I
I
I
1 stall cycle
1 issue cycle
1 issue cycle
2-cycle latency for I-stage of branch destination
1 stall cycle
EX
EX
EX
SX
EX
EX
EX
EX
EX
D
D
D
D
—
D
I
...
...
NA
EX
MA
SX
NA
MA
NA
NA
EX
NA
NA
NA
—
D
D
...
NA
NA
SX
NA
—
D
S
S
S
S
S
S
S
S
S
I
i
4 issue cycles
...
SX
NA
S
S
D
S
MA
Rev.7.00 Oct. 10, 2008 Page 245 of 1074
E
S
S
A
EX-group SHAD and EX-group ADD
cannot be executed in parallel. Therefore,
SHAD is issued first, and the following
ADD is recombined with the next
instruction.
EX-group ADD and LS-group MOV.L can
be executed in parallel. Overlapping of
stages in the 2nd instruction is possible.
AND.B and MOV are fetched
simultaneously, but MOV is stalled due to
resource locking. After the lock is released,
MOV is refetched together with the next
instruction.
No stall occurs if the branch is not taken.
If the branch is taken, the I-stage of the
branch destination is stalled for the period
of latency. This stall can be covered with a
delay slot instruction which is not parallel-
executable with the branch instruction.
Even if the BT/BF branch is taken, the I-
stage of the branch destination is not
stalled if the displacement is zero.
S
Section 8 Pipelining
REJ09B0366-0700