HD6417750RF240DV Renesas Electronics America, HD6417750RF240DV Datasheet - Page 832

MPU 3V 16K I-TEMP,PB-FREE 208-QF

HD6417750RF240DV

Manufacturer Part Number
HD6417750RF240DV
Description
MPU 3V 16K I-TEMP,PB-FREE 208-QF
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417750RF240DV

Core Processor
SH-4
Core Size
32-Bit
Speed
240MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
28
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
208-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417750RF240DV
Manufacturer:
HITACHI
Quantity:
7 287
Section 16 Serial Communication Interface with FIFO (SCIF)
SCFCR2 performs data count resetting and trigger data number setting for the transmit and receive
FIFO registers, and also contains a loopback test enable bit.
SCFCR2 can be read or written to by the CPU at all times.
SCFCR2 is initialized to H'0000 by a power-on reset or manual reset. It is not initialized in
standby mode or in the module standby state.
Bits 15 to 11—Reserved: These bits are always read as 0, and should only be written with 0.
Bits 10 to 8 (SH7750)—Reserved: These bits are always read as 0, and should only be written
with 0.
Bits 10 to 8 (SH7750S, SH7750R)—RTS2 Output Active Trigger (RSTRG2, RSTG1, and
RSTG0): These bits output the high level to the RTS2 signal when the number of received data
stored in the receive FIFO data register (SCFRDR2) exceeds the trigger number, as shown in the
table below.
Bit 10: RSTRG2
Rev.7.00 Oct. 10, 2008 Page 746 of 1074
REJ09B0366-0700
0
1
Bit 9: RSTRG1
0
1
0
1
Bit 8: RSTRG0
1
0
1
0
1
0
1
0
RTS2 Output Active Trigger
15
1
4
6
8
10
12
14
(Initial value)

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