HD6417750RF240DV Renesas Electronics America, HD6417750RF240DV Datasheet - Page 775
HD6417750RF240DV
Manufacturer Part Number
HD6417750RF240DV
Description
MPU 3V 16K I-TEMP,PB-FREE 208-QF
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417750RBP240DV.pdf
(1164 pages)
Specifications of HD6417750RF240DV
Core Processor
SH-4
Core Size
32-Bit
Speed
240MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
28
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
208-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417750RF240DV
Manufacturer:
HITACHI
Quantity:
7 287
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Section 15 Serial Communication Interface (SCI)
Clock
Either an internal clock generated by the on-chip baud rate generator or an external clock input at
the SCK pin can be selected as the SCI's serial clock, according to the setting of the C/A bit in
SCSMR1 and the CKE1 and CKE0 bits in SCSCR1. For details of SCI clock source selection, see
table 15.9.
When an external clock is input at the SCK pin, the clock frequency should be 16 times the bit rate
used.
When the SCI is operated on an internal clock, the clock can be output from the SCK pin. The
frequency of the clock output in this case is equal to the bit rate, and the phase is such that the
rising edge of the clock is at the center of each transmit data bit, as shown in figure 15.6.
0
D0
D1
D2
D3
D4
D5
D6
D7
0/1
1
1
One frame
Figure 15.6 Relation between Output Clock and Transfer Data Phase
(Asynchronous Mode)
Data Transfer Operations
SCI Initialization (Asynchronous Mode): Before transmitting and receiving data, it is necessary
to clear the TE and RE bits in SCSCR1 to 0, then initialize the SCI as described below.
When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to
0 before making the change using the following procedure. When the TE bit is cleared to 0, the
TDRE flag is set to 1 and SCTSR1 is initialized. Note that clearing the RE bit to 0 does not change
the contents of the RDRF, PER, FER, and ORER flags, or the contents of SCRDR1.
When an external clock is used the clock should not be stopped during operation, including
initialization, since operation will be unreliable in this case.
Figure 15.7 shows a sample SCI initialization flowchart.
Rev.7.00 Oct. 10, 2008 Page 689 of 1074
REJ09B0366-0700
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